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| PRELIMINARY DATA SHEET MICRONAS INTERMETALL TPU 3035, TPU 3040 Teletext Processors MICRONAS Edition Dec. 9, 1996 6251-349-5PD TPU 3035, TPU 3040 Contents Page 4 4 6 6 7 7 8 8 8 9 9 9 10 10 11 12 13 14 15 15 15 16 16 16 16 17 17 17 18 18 19 19 19 20 20 21 22 Section 1. 1.1. 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 2.7. 2.8. 2.9. 3. 3.1. 3.2. 3.3. 3.4. 3.5. 3.6. 3.6.1. 3.6.2. 3.6.3. 3.6.4. 3.6.5. 3.6.6. 3.6.7. 3.6.8. 3.6.9. 3.6.10. 3.6.11. 3.6.12. 3.6.13. 3.6.14. 3.6.15. 3.6.15.1. 3.6.15.2. 3.6.16. Title Introduction Features Functional Description Conceptional Overview Teletext Acquisition Teletext Page Management Display Page Generation WST Display Controller Character Generator OSD Layer DRAM Interface Applications Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Pin Configuration Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Crystal Characteristics General Operating Conditions General Input Characteristics Power Consumption Timer, Interrupt and Watchdog Characteristics Clock Generator Characteristics Video Interface Characteristics MAC Interface Characteristics RGB Interface Characteristics Prio & Color Interface Characteristics H&V Sync Interface Characteristics MSync Interface Characteristics I2C-Bus Interface Characteristics DRAM Interface Characteristics Fast Mode Timing Slow Mode Timing Waveforms PRELIMINARY DATA SHEET 2 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 Contents, continued Page 23 23 23 24 24 25 25 25 26 27 29 30 31 32 36 37 44 44 45 47 48 49 50 63 64 64 64 65 66 66 67 68 68 72 Section 4. 4.1. 4.1.1. 4.2. 4.2.1. 4.2.1.1. 4.2.1.2. 4.2.1.3. 4.2.1.4. 4.3. 4.4. 4.5. 4.6. 4.7. 4.8. 4.9. 4.10. 4.11. 4.12. 4.13. 4.14. 4.15. 4.16. 5. 6. 6.1. 6.2. 6.3. 6.4. 6.5. 6.6. 7. 8. 9. Title Definitions CPU Memory Mapping I2C-Bus Interface Subaddressing CPU Subaddressing DRAM Subaddressing Command Subaddressing Data Subaddressing Display Memory OSD Layer Character Set Font Structure Character Font Character Mapping Command Language Memory Manager Memory Organization Page Table Ghost Row Organization Subpage Manager I/O Page Definition I/O Page Register Application Emulator EMU Additional Pin Connections EMU Pin Configuration EMU Pin Connections EMU I/O Page Definition EMU I/O Page Register EMU Board Glossary of Abbreviations References Data Sheet History MICRONAS INTERMETALL 3 TPU 3035, TPU 3040 Multistandard Teletext Processor for Level 1 and 2 Note: This data sheet describes functions and characteristics of TPU3040 TC25. PRELIMINARY DATA SHEET If not otherwise designated, the pin numbers mentioned refer to the 44-pin PLCC package. For corresponding PDIP numbers see page 11. Revision bars indicate significant changes to the previous version. 1. Introduction The TPU 3040 is a single chip World System Teletext (WST) decoder for applications in analog and digital TV sets. Based on a 65C02 core with RAM and ROM on chip, an adaptive data slicer, a display controller and a number of interfaces, the TPU 3040 offers acquisition and display of various teletext and data services such as WST, PDC, VPS and WSS. 1.1. Features The TPU 3040 is an integrated circuit designed in CMOS technology. As a stand-alone system or in combination with the DIGIT 3000 system, the TPU 3040 offers a wide range of new and interesting features, some of them unique in comparison with other products on the market. The TPU 3035 is a stripped-down version of TPU 3040, designed for low-cost applications. The basic chip architecture remains unchanged, whereas some of the more sophisticated features are removed (see Tab 1-1). In the following description only the TPU 3040 is mentioned. Table 1-1: Feature List TPU Acquisition No. of analog comp. video inputs Clamping AGC Sync. separation with PLL Adaptive data slicer Signal quality detection PAL VBI acquisition NTSC VBI acquisition MAC VBI acquisition (PLCC44 only) MAC packet text acquisition (PLCC44 only) Full-field acquisition Asynchronous acquisition & display Ghost row acquisition EPG support Internal row 26 processing (Extended Character Sets) FLOF/TOP s/w support on chip PDC acquisition VPS acquisition WSS acquisition US captioning Software acquisition (advanced header, magazine shuffle, ...) Full parallel acquisition 1 x x x x x x - - - - x x - - x x x - - x x 2 x x x x x x - x - - x x x x x x x x x x x 3035 3040 4 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 Table 1-1, continued TPU Display No. of different characters No. of national language char. sets Character matrix size No. of display rows Pixel graphics 16:9 display (25% shrink) 1/2 screen display (50% shrink) 1/2 screen 16:9 display (62.5% shrink) 32 kHz mode Noninterlace display 50/60 Hz display 100/120 Hz display Scrolling vertical Scrolling horizontal Double height page display Status row single height Two page display side by side Stable (line locked) display with noisy video Display synchronized by input video 75 Ohm output Half contrast RGB out RGB level adjustable (externally) Level 3 Level 2 Level 2 Level 2 Level 2 DRCS CLUT double width double height full screen color 512 16 10x10 > 26 - - - - - x x - x - x x - x - - x - - (D3000) x x x x (D3000) x - 512 16 10x10 > 26 - x x x x x x x x - x x - x - - Technology x - - (D3000) x x x x (D3000) x - No. of pages on-chip No. of pages off-chip Minimum DRAM (ext.) Maximum DRAM (ext.) DRAM organization DRAM access (ns, page mode) Automatic memory/config. check Var. no. of subpages (internal subpage management) Constant page access time Dyn. pg. storage (data compression) General Product Info Supply voltage [V] Power dissipation [mW] Control bus IR decoder and control Software macro interface System clock [MHz] Package No. of ICs for complete solution (without external DRAM) 5 250 I2C - x 20.25 PDIP40 1 0.8 m CMOS 5 250 I2C - x 20.25 PLCC44 PDIP40 1 0.8 m CMOS 3035 3040 TPU Memory 3035 3040 - 112 256 Kbit 1 Mbit 1 bit 90 x x x - - 2032 256 Kbit 16 Mbit 1 bit 90 x x x - OSD - layer independent Display priority via software-ID RGB input from SCART and Fast Blank interface Hardware cursor MICRONAS INTERMETALL 5 TPU 3035, TPU 3040 2. Functional Description 2.1. Conceptional Overview The basic idea behind the TPU 3040 concept is the replacement of random logic by software. The still existing hardware supports the on-chip CPU in tasks with high data rates and ineffective software solutions. Typical tasks of a teletext decoder are listed below (realization on TPU 3040 in brackets): - teletext data acquisition - teletext data decoding - page generation - page memory management - page display - user interface (hardware) (software) (software) (software) (hardware) (software) PRELIMINARY DATA SHEET cessing this scratch buffer, the CPU stores reorganized teletext lines into the page memory which takes up the greatest space in the DRAM capacity. A third part of the DRAM holds WST level 2 display data, which are read out by the WST layer. The CPU has to generate the display data by decoding teletext information from the page memory. Apart from the WST layer, there is also one additional on-chip OSD layer. The OSD layer accesses the on-chip memory to read text and character font information. The RGB outputs of the OSD layer can have higher priority than the WST layer outputs. Thus it is possible to overlay the teletext display with an additional layer for user guidance. The CPU memory contains RAM, program ROM and character ROM. The character ROM holds the font data and is separated from the program ROM to save CPU time. The CPU can still access the character ROM via a DMA interface including wait cycles. The WST layer and the additional OSD layer can also access the CPU memory via the same DMA interface. The CPU is supported by some glue logic such as timer, watchdog and interrupt controller and communicates with the outside world via the I2C-Bus. Fig. 2-1 shows the functional block diagram of the TPU 3040. The software approach is realized using a 65C02 core with RAM and program ROM on chip. Via I/O the CPU is connected to a DRAM interface. The DRAM contains an acquisition scratch buffer which is filled automatically by the teletext slicer circuit. After pro- 6 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 1 22 23 24 43 TPU 3040 42 44 MUX Clamping AGC ADC Slicer 7-18 3 4 19 I2C-Bus Interface Program RAM Program ROM 65C02 DRAM Interface 5 20 6 21 2 29 Timer Interrupt Watchdog Skew Delay DMA Interface WST Layer 27 28 Clock Generator Sync Interface Character ROM OSD Layer RGB & PRIO Interface 36 37 38 39 25 26 41 40 34 35 30 31 32 33 Fig. 2-1: Functional block diagram of TPU 3040 2.2. Teletext Acquisition The only task of the slicer circuit is to extract teletext lines from the incoming composite video signal and to store them into the acquisition scratch buffer of the external DRAM. No page selection is done at this hardware level. Two analog sources can be connected, thus it is possible to receive text from one channel while watching another on the screen. After clamping and AGC amplifier the analog video signal is converted into binary data. Sync separation is done by a sync slicer and a horizontal PLL, which generate the horizontal and vertical timing. By these means no external sync signals are needed and any available signal source can be used for teletext reception. The teletext information itself is acquired using adaptive slicers on bit and byte level with soft error detection to decrease the bit error rate under bad reception condiMICRONAS INTERMETALL tions. The slicer can be programmed to different bit rates for reception of PAL, NTSC or MAC world system teletext as well as VPS,WSS or CAPTION signals. 2.3. Teletext Page Management As a state-of-the-art teletext decoder the TPU 3040 is able to store and manage a sufficient number of teletext pages to absorb the annoying transmission cycle times. The number of available pages is only limited by the memory size. With an intelligent software and a 16 Mbit DRAM it is possible to store and to control more than 2000 teletext pages. The management of such a data base is a typical software task and is therefore performed by the 65C02. Using a fixed length page table with one entry for every possible page, the software distributes the content of the acquisition scratch buffer among the page memory. The page size is fixed to 1 KByte, only ghost rows are 7 TPU 3035, TPU 3040 chained in 128-byte segments to avoid unused memory space. PRELIMINARY DATA SHEET To present a WST level 2 display, the teletext display controller has to evaluate the following attributes in parallel, that is for every character location: - 10-bit character code - 5-bit foreground color 2.4. Display Page Generation A stored teletext page cannot be displayed directly, because of the row-adaptive transmission and the level 2 enhancements (row 26-29). Therefore the CPU has to generate a display page buffer, separated into level 1 data such as character codes and spacing attributes and into level 2 data, such as character set extension and non-spacing attributes. This is done by using a slightly modified stack model, in which one pointer bit for every character location indicates the presence of additional parallel attributes. Fig. 2-2 shows the organization of the stack row buffer. In this stack model the number of nonspacing attributes per row is limited to 40, which agrees with the WST and CEPT specification. - 5-bit background color - 2-bit size - 5-bit flash - 1-bit invert - 1-bit separated - 1-bit conceal - 1-bit underline - 1-bit boxing/window Additional attributes are defined to improve the display of CAPTION and OSD text: - 1-bit italics - 1-bit shadow The display controller delivers 5-bit digital color information, a shadow signal for contrast reduction and a fast blank signal. The color bus can be used to address external color-look-up-tables (CLUT) which are part of modern digital TV systems, such as the DIGIT 3000. By this means, the full level 2 color spectrum can be displayed. For simple level 1 applications only 3 bits of the color bus are converted into analog RGB signals on chip. 2.6. Character Generator Characters are displayed with a 10x10 pixel resolution in PAL and 10x8 pixel resolution in NTSC mode. Pixel clock is 10.125 MHz, derived from the main clock of 20.25 MHz. To get 10-bit pixel information two memory cycles are needed. The character font is part of the mask-programmable ROM, but supplied with its own bus structure (see Fig. 4-1). By this means the data transfer between character ROM and teletext display controller does not stop the CPU, which is important in the case of doubled line frequency. Both bus structures are connected via a memory interface which allows cross-connections using DMA or wait cycles. As the number of addressable characters is 1024, the maximum character font size is 12800 byte. In this case part of the character font can be shifted into the program ROM which causes DMA cycles. Therefore only less frequently used characters should be placed into the program ROM. Vice versa seldom used CPU code can be put into the character ROM. The WST specification defines a number of 7-bit code tables, which are filled with 96 characters only. In the G0 code table some characters have several language deMICRONAS INTERMETALL Level 2 Buffer 1 1 1 0 1 1 0 1 1 1 Char 3 Attr. Char 3 Attr. Char 3 Attr. Char 3 Attr. Char 6 Attr. Char 6 Attr. Char 6 Attr. Char 10 Attr. Char 10 Attr. Char 10 Attr. Pointer 0 0 1 0 0 1 0 0 0 1 Level 1 Buffer Char 1 Char 2 Char 3 Char 4 Char 5 Char 6 Char 7 Char 8 Char 9 Char 10 0 0 0 0 0 Char 36 Attr. 1 0 0 0 0 Char 36 Char 37 Char 38 Char 39 Char 40 Fig. 2-2: Stack Row Buffer 2.5. WST Display Controller The display controller includes two row buffers. The first row buffer holds a copy of a teletext row from the display page buffer. This decreases the data rate through the DRAM interface by a factor of 10 or 8, because new teletext row data is needed only after 10 lines in PAL or 8 lines in NTSC mode. The second row buffer stores all display attributes in parallel, to allow level 2 display without additional decoding. 8 PRELIMINARY DATA SHEET TPU 3035, TPU 3040 time faster than 120 ns. The data rate calculation already takes into account the required refresh cycles. The DRAM interface has to handle 3 asynchronous data streams. The CPU needs access to every memory location of the DRAM. During VBI the slicer writes up to 22 teletext lines of 43 bytes into the acquisition scratch memory. Alternatively the slicer can store MAC packets of 90 bytes into the acquisition scratch. During text display the display controller copies teletext rows from display memory into its internal row buffer. The lower data rate of the slow mode makes some restrictions necessary. With 6.1 Mbit/s it is no longer possible to run slicer and display in parallel. Only MAC packet teletext can still be acquired asynchronously because of the lower bit rate. VBI teletext can only be acquired while the display controller is inactive (synchronous acquisition and display). 2.9. Applications The field of applications covers analog and digital TV sets, set-top satellite decoders, video recorders and home computers. For example, Fig. 2-4 shows how the TPU 3040 fits into an analog environment. Two analog sources are connected and the output is analog RGB, synchronized with an external sync signal or self-timed. Page selection and other user actions are sent to the TPU 3040 via I2C-Bus using a high level command language. pendent variations. Additionally characters from the G0 code table can be combined with diacritical marks from the G2 code table (row 26). Thus it is not possible to simply transform the code tables into a continuous font ROM without getting unused ROM space and multiple defined character fonts. The character ROM is optimized by reorganizing the code table structure of the WST specification. The whole character font is subdivided into blocks of 32 characters which are mapped to the WST character sets via a mask programmable mapping ROM (see Fig. 4-5). The character set selection is done via software. 2.7. OSD Layer Apart from the WST layer, there is also one additional OSD layer on chip. The OSD layer accesses the CPU memory via DMA to read text and character font information. The RGB outputs of the OSD layer can have higher priority than the WST layer outputs. Thus it is possible to overlay the teletext display with an additional layer for user guidance (see Fig. 2-3). Full Screen Layer WST Layer DRAM OSD Layer Tuner 1 Fig. 2-3: Display Layer TPU 3040 R G B 2.8. DRAM Interface The DRAM interface connects a standard DRAM to the internal bus structure. The address bus is 12 bit wide, addressing DRAMs up to 16 Mbit. Smaller DRAMs can also be connected. The maximum data throughput of the DRAM interface is 8.82 Mbit/s. This fast mode timing is adapted to DRAMS with page mode cycle time faster than 85 ns. In slow mode the data rate is 6.1 Mbit/s and the timing is adapted to DRAMS with a page mode cycle Tuner 2 I2C-Bus Controller Sync Fig. 2-4: Stand-Alone Application MICRONAS INTERMETALL 9 TPU 3035, TPU 3040 3. Specifications 3.1. Outline Dimensions PRELIMINARY DATA SHEET Fig. 3-1: 40-pin Plastic Dual-Inline Package (PDIP40) Weight approx. 6 g Dimensions in mm 2.35 1+0.2 x 45 6 7 1.6 2 17.4+0.25 6 16.5 0.1 0.711 1 40 39 0.457 10 x 1.27 = 12.7 0.1 1.27 0.1 1.2 x 45 2.35 2 8.6 5 17 18 17.4 +0.25 28 29 1.9 1.5 4.05 4.75 0.15 0.254 0.05 0.1 16.5 0.1 Fig. 3-2: 44-Pin Plastic Leaded Chip Carrier Package (PLCC44) Weight approximately 2.5 g Dimensions in mm 10 10 x 1.27 = 12.7 0.1 1.27 0.1 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 3.2. Pin Connections and Short Descriptions Pin No. 44-pin PLCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin No. 40-pin PDIP 1 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 - - - 20 Signal Name Reference Voltage Top Test Mode DRAM Data DRAM Write Enable DRAM Row Address Strobe DRAM Column Address Strobe DRAM Address 0 DRAM Address 1 DRAM Address 2 DRAM Address 3 DRAM Address 4 DRAM Address 5 DRAM Address 6 DRAM Address 7 DRAM Address 8 DRAM Address 9 DRAM Address 10 DRAM Address 11 IIC Bus Clock IIC Bus Data Infrared MAC Paket Data MAC VBI Data MAC Sync Horizontal Sync Composite Sync 1 Main Sync Vertical Sync Composite Sync 2 Crystal Oscillator Output Crystal Oscillator Input Main Clock Reset Fast Blank Input Shadow Priority Bus 0 Analog Blue Input Priority Bus 1 Analog Green Input Priority Bus 2 Analog Red Input Color Address Bus 4 Digital Supply Voltage Type Supply Input Input/Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input/Output Input/Output Input Input Input Input Input/Output Output Input Input/Output Output Output Input Input Input/Output Input Output Input/Output Input Input/Output Input Input/Output Input Output Supply Symbol VRT TEST DATA WE RAS CAS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 SCL SDA IR MAC_PAK MAC_VBI MAC_SYNC HSYNC CSYNC1 MSYNC VSYNC CSYNC2 XTAL2 XTAL1 CLK20 RESET FBIN SHADOW PRIO0 BIN PRIO1 GIN PRIO2 RIN COLOR4 DVSUP 26 27 28 29 30 19 18 17 16 15 31 32 33 34 14 13 12 11 MICRONAS INTERMETALL 11 TPU 3035, TPU 3040 Pin Connections and Short Descriptions, continued Pin No. 44-pin PLCC 35 36 Pin No. 40-pin PDIP 10 9 Signal Name Type PRELIMINARY DATA SHEET Symbol Digital Ground Fast Blank Output Color Address Bus 3 Analog Blue Output Color Address Bus 2 Analog Green Output Color Address Bus 1 Analog Red Output Color Address Bus 0 Analog Ground Analog Supply Voltage Analog Composite Video 1 Analog Signal Ground Analog Composite Video 2 Supply Output Output Output Output Output Output Output Output Supply Supply Input Supply Input DGND FBOUT COLOR3 BOUT COLOR2 GOUT COLOR1 ROUT COLOR0 AGND AVSUP VIN1 SGND VIN2 37 8 38 7 39 6 40 41 42 43 44 5 4 3 2 - 3.3. Pin Descriptions Pin 1 - VRT Reference Voltage Top (Fig. 3-5) This pin is connected to the internally-stabilized reference voltage of the A/D converter which is derived from the VASUP supply. Pin 1 must be decoupled externally to prevent high and low frequency noise. Pin 2 - TEST Test Input (Fig. 3-6) This pin is used for switching the TPU 3040 into test mode. For normal operation this pin has to be connected to ground. Pin 3 - DATA DRAM Data Input/Output (Fig. 3-7) This pin serves as an output for writing data into the external DRAM and as an input for reading data from the external DRAM. Pin 4 - WE DRAM Write Enable Output (Fig. 3-7) This pin supplies the Write Enable signal to the external DRAM. Pin 5 - RAS DRAM Row Address Strobe Output (Fig. 3-7) This pin supplies the Row Address Strobe signal to the external DRAM. Pin 6 - CAS DRAM Column Address Strobe Output (Fig. 3-7) This pin supplies the Column Address Strobe signal to the external DRAM. Pins 7 to 18 - A0 to A11 DRAM Address Outputs (Figs. 3-7 and 3-8) These pins are used for addressing the external DRAM. 12 The addressing is compatible to all DRAM sizes from 64K to 16M, therefore the correct connection of pins A8 to A11 to the corresponding DRAM pins is necessary. Pins 19 and 20 - SCL and SDA IIC Bus (Fig. 3-9) Via these pins, the TPU 3040 communicates with external devices. Pin 21 - IR Infrared (Fig. 3-10) Via this pin the TPU 3040 can receive remote control signals. Pin 22 - MAC_PAK MAC Paket Data (Fig. 3-10) Via this pin, the TPU 3040 receives MAC packets from the DMA 2381 or from the DMA 2386. Pin 23 - MAC_VBI MAC VBI Data (Fig. 3-10) By means of this input, the TPU 3040 receives MAC VBI data from the DMA 2381 or from the DMA 2386. Pin 24 - MAC_SYNC MAC Synchronization (Fig. 3-10) By means of this input, the TPU 3040 receives the required MAC synchronization pulse from the DMA 2381. This sync pulse is used both as line sync and frame sync for the MAC teletext acquisition. Pin 25 - HSYNC Horizontal Synchronization (Fig. 3-7) Via this input, the TPU 3040 receives the horizontal synchronization signal. Either the falling or the rising edge of this signal will start the internal horizontal timing generation. Pin 26 - VSYNC Vertical Synchronization (Fig. 3-7) Via this input, the TPU 3040 receives the vertical synchronization signal. Either the falling or the rising edge of this signal will start the internal vertical timing generation. MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 3.4. Pin Configuration Pin 27 and 28 - XTAL1 and XTAL2 (Fig. 3-11) These oscillator pins are used to connect a 20.25MHz crystal, which determines the internal clock signal. Alternatively, an 20.25MHz clock signal may be fed to pin 28. Pin 29 - RESET Reset Input/Output (Fig. 3-9) This pin is used for hardware reset. The TPU 3040 watchdog generates a reset pulse which can be used to reset external circuits. Pin 30 - FBIN Fast Blanking Input (Fig. 3-12) This pin serves for enabling the analog RGB inputs. Pin 31 to 33 - RIN, GIN, BIN RGB Inputs (Fig. 3-13) Via these inputs, the TPU 3040 receives analog RBG signals, e.g. OSD or video recorder (SCART), which are fed to the analog RBG outputs. The specified level of these signals is 0 V to 0.7 V. For other DC levels, an AC coupling has to be used and the internal clamping circuit will adjust the DC level. Pin 34 - DVSUP Digital Supply Voltage This pin supplies all digital stages and has to be connected with the positive supply voltage. Pin 35 - DGND Digital Ground This pin is the common ground connection of all digital stages and has to be connected with the ground of the power supply. Pin 36 - FBOUT Fast Blanking Output (Fig. 3-8) This output supplies a fast switching signal, indicating the presence of RBG output signals. Pin 37 to 39 - ROUT, GOUT, BOUT RGB Outputs (Fig. 3-13) These outputs either supply the analog RGB signals, which have been received via the analog RGB input pins 31 to 33, or the internally generated RGB signals. Pin 40 - AGND Analog Ground This pin is the common ground connection of all analog stages and has to be connected with the ground of the power supply. Pin 41 - AVSUP Analog Supply Voltage This pin supplies all analog stages and has to be connected with the positive supply voltage. Pin 42 and 44 - VIN1 and VIN2 Analog Video Inputs (Fig. 3-14) The analog input signals carrying text data are fed to the TPU 3040 via a clamping capacitor of 33nF to these pins. Pin 43 - SGND Signal Ground The lower end of the internal reference chain of the A/D converter is internally connected to the pin 43. VRT SGND VIN1 AVSUP AGND ROUT / COLOR0 GOUT / COLOR1 BOUT / COLOR2 FBOUT / COLOR3 DGND DVSUP RIN / COLOR4 GIN / PRIO2 BIN / PRIO1 FBIN / PRIO0 RESET XTAL1 / CLK20 XTAL2 VSYNC / CSYNC HSYNC / MSYNC 1 2 3 4 5 6 7 40 39 38 37 36 35 34 TEST DATA WE RAS CAS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 SCL SDA IR TPU 3040 VRT 8 9 10 11 12 13 14 15 16 17 18 19 20 33 32 31 30 29 28 27 26 25 24 23 22 21 Fig. 3-3: TPU 3040 in 40-pin PDIP package TEST DATA WE RAS CAS VIN2 SGND VIN1 AVSUP AGND A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 7 8 9 10 11 12 13 14 15 16 17 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 ROUT / COLOR0 GOUT / COLOR1 BOUT / COLOR2 FBOUT / COLOR3 DGND DVSUP RIN / COLOR4 GIN / PRIO2 BIN / PRIO1 FBIN / PRIO0 RESET TPU 3040 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 A11 SCL SDA IR MAC_PAK MAC_VBI XTAL1 / CLK20 XTAL2 VSYNC / CSYNC HSYNC / MSYNC MAC_SYNC Fig. 3-4: TPU 3040 in 44-pin PLCC package MICRONAS INTERMETALL 13 TPU 3035, TPU 3040 3.5. Pin Circuits The following figures schematically show the circuitry at the various pins. The integrated protection structures are not shown. The letter "P" means P-channel, the letter "N" N-channel. Poff PRELIMINARY DATA SHEET Fig. 3-10: Input Pins 22 to 24 - + = VRef Fig. 3-5: Supply Pin 1 VSUP P Poff Fig. 3-11: Output/Input Pins 27, 28 N GND Fig. 3-6: Input Pins 2 and 21 = 0.7 V VSUP P P Fig. 3-12: Input Pin 30 N N GND Fig. 3-7: Input/Output Pins 3 to 14, 18, 25, 26 Fastblank 0.7 V = = 0.46 V Clamp VSUP P Fig. 3-13: Input/Output Pins 31 to 33 and 37 to 39 N GND Fig. 3-8: Output Pins 15 to 17 and 36 Fig. 3-9: Input/Output Pins 19, 20 and 29 Fig. 3-14: Input Pins 42 and 44 MICRONAS INTERMETALL 14 PRELIMINARY DATA SHEET TPU 3035, TPU 3040 3.6. Electrical Characteristics All voltages refer to ground. 3.6.1. Absolute Maximum Ratings Symbol TA TS VDSUP VASUP VDI VAI IO Parameter Ambient Operating Temperature Storage Temperature Digital Supply Voltage Analog Supply Voltage Digital Input Voltage Analog Input Voltage Output Current Pin No. - - 34 41 Min. 0 *40 *0.3 *0.3 *0.3 *0.3 *10 Max. 65 125 6 6 VDSUP )0.3 VASUP )0.3 10 Unit C C V V V V mA Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 3.6.2. Recommended Crystal Characteristics Symbol TA f0 f f0 f f Parameter Ambient Operating Temperature Parallel Resonance Frequency Frequency Tolerance Pin No. 27, 28 Min. 0 - - Typ. - 20.25 - Max. 65 - 50 50 Unit C MHz ppm CL = 30 pF, TA = 25 C TA = 25 C over operating temperature range with respect to frequency at 25 C Test Conditions Frequency Deviation Temperature versus - - ppm Rr C0 C1 PD f0 fH Series Resistance Static Capacitance Dynamic Capacitance Rated Drive Level Spurious Frequency Attenuation - - 10 - 3 - - - 0.2 - 30 8 30 - - pF fF mW dB MICRONAS INTERMETALL 15 TPU 3035, TPU 3040 3.6.3. General Operating Conditions Symbol TA VDSUP VASUP fCLK Parameter Ambient Operating Temperature Digital Supply Voltage Analog Supply Voltage Clock Frequency Pin No. all 34 41 27, 28 Min. 0 4.75 4.75 20.20 Typ. 20 5.0 5.0 20.25 Max. 65 5.25 5.25 20.30 PRELIMINARY DATA SHEET Unit C V V MHz Test Conditions correct slicer operation 3.6.4. General Input Characteristics Symbol II CI Parameter Input Leakage Current Input Capacitance Pin No. all inputs Min. Typ. Max. 1 20 Unit A pF Test Conditions VGND VI VSUP 3.6.5. Power Consumption Symbol IDSUP IASUP PT Parameter Digital Supply Current Analog Supply Current Total Power Consumption Pin No. 34 41 34,41 Min. - - - Typ. 40 20 300 Max. 60 30 500 Unit mA mA mW Test Conditions 3.6.6. Timer, Interrupt and Watchdog Characteristics Symbol VIL VIH VOL tOL VIL VIH VIL VIH Parameter Reset Input Low Voltage Reset Input High Voltage Reset Output Low Voltage Reset Output Pulse Width Test Input Low Voltage Test Input High Voltage Infrared Input Low Voltage Infrared Input High Voltage 21 2 Pin No. 29 Min. - 3.0 - - - 2.0 - 2.0 Typ. - - - 1.618 - - - - Max. 1.5 - 0.4 - 0.8 - 0.8 - Unit V V V ms V V V V IL = 3mA 215 / fCLK Test Conditions 16 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 3.6.7. Clock Generator Characteristics Symbol VCLK fCLK fCLK Parameter Clock Input Amplitude Clock Input Frequency Generated Clock Frequency 27,28 Pin No. 28 Min. 1.0 20.20 20.20 Typ. - 20.25 20.25 Max. 3.0 20.30 20.30 Unit VPP MHz MHz recommended crystal Test Conditions CC = 10 nF 3.6.8. Video Interface Characteristics Symbol VVRT VVRTN VI ICLP ICLN ICR CC RD Parameter Voltage Reference Top Voltage Reference Top Noise Video Input Voltage Positive Clamping Current Negative Clamping Current Clamping Current Ratio Recommended Coupling Capacitance Recommended Drive Impedance 42, 44 Pin No. 1 Min. 2.6 - 0.7 - - 35 - Typ. 2.8 - 1 235 6 40 33 Max. 3.0 100 1.3 - - 45 - nF Unit V mVPP VPP A A Test Conditions CL = 100 nF || 10 F CL = 100 nF || 10 F RD= 75 VIN = 0V VIN = VASUP - 75 100 3.6.9. MAC Interface Characteristics Symbol VIL VIH Parameter Input Low Voltage Input High Voltage Pin No. 22, 23, 24 Min. - 2.0 Typ. - - Max. 0.8 - Unit V V Test Conditions MICRONAS INTERMETALL 17 TPU 3035, TPU 3040 3.6.10. RGB Interface Characteristics Symbol VI CC RCL VIL VIH VOL VOH100 VOH66 VO tT VOHO VOLO Ron VOL VOH tT Parameter RGB Input Voltage External Coupling Capacitance RGB Input Resistance during Clamping Fast Blank Input Low Voltage Fast Blank Input High Voltage RGB Output Low Voltage RGB Output High Voltage RGB Output High Voltage Differential RGB Output Voltage RGB Output Transition Time RGB Output Positive Overshoot RGB Output Negative Overshoot Resistance from RGB Inputs to RGB Outputs Fast Blank Output Low Voltage Fast Blank Output High Voltage Fast Blank Output Transition Time Differential RGB & FB Timing 36 37,38,39 31, 32, 33, 37, 38, 39 36 - - 37, 38, 39 30 Pin No. 31, 32, 33 Min. 0 100 - Typ. 0 to 0.7 - Max. 1.5 1000 100 PRELIMINARY DATA SHEET Unit V nF Test Conditions RL = 75 RL > 100k clamp window = 64 s RL = 75 RL = 75 VASUP = 5.0 V, IL = 0.5 mA VASUP = 5.0 V, IL = *0.5 mA VASUP = 5.0 V, IL = *0.5 mA VASUP = 5.0 V, ILt10 A VASUP = 5.0 V, CL = 20 pF VASUP = 5.0 V, CL = 20 pF VASUP = 5.0 V, CL = 20 pF ext. RGB on - 0.9 0 630 420 - - - - - 700 467 - - 0.5 - 50 770 513 50 10 10 10 V V mV mV mV mV ns % % 150 - 3.0 - - - - 0.4 - 10 V V ns IL = 1.6 mA IL =*0.5 mA CL = 20 pF VOL(max) VOH(min) CL = 20 pF tD 10 ns 3.6.11. Prio & Color Interface Characteristics Symbol VIL VIH VOL Parameter Prio Input Low Voltage Prio Input High Voltage Prio & Color Output Low Voltage 30 to 33 36 to 39 Pin No. 30 to 32 Min. - 1.5 - Typ. - - 0.25 Max. 0.8 - 0.5 Unit V V V IL = 8mA, strength 3 IL = 6mA, strength 2 IL = 4mA, strength 1 IL = 2mA, strength 0 IL = *0.01 mA VOL = 0 V CL = 20 pF CL = 20 pF Test Conditions VOH IO tT tD Prio & Color Output High Voltage Prio & Color Output Pull-up Current Prio & Color Output Transition Time Differential Prio & Color Timing 1.8 1.3 2.0 1.5 - - V mA - - 10 ns 10 ns 18 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 3.6.12. H&V Sync Interface Characteristics Symbol VITF VITR VITH VOL VOH tT Parameter Input Trigger Level High Low Input Trigger Level Low High Input Trigger Hysteresis Output Low Voltage Output High Voltage Output Transition Time Pin No. 25, 26 Min. 1.5 Typ. - Max. 2.0 Unit V Test Conditions 2.5 - 3.0 V 0.5 - 2.4 - - - - - - 0.4 - 10 V V V ns IL = 1.6 mA IL =*0.1 mA CL = 20 pF 3.6.13. MSync Interface Characteristics Symbol VIL VIH tIS tIH Parameter Input Low Voltage Input High Voltage Input Setup Time Input Hold Time Pin No. 25 Min. - 1.5 10 0 Typ. - - - - Max. 0.8 - - - Unit V V ns ns CL = 20 pF CL = 20 pF Test Conditions 3.6.14. I2C-Bus Interface Characteristics Symbol VITF VITR VITH VOL tR tF fSCL Parameter Input Trigger Level High Low Input Trigger Level Low High Input Trigger Hysteresis Output Low Voltage Input Rise Time Output Fall Time Clock Frequency 19 Pin No. 19, 20 Min. 1.5 Typ. - Max. 2.0 Unit V Test Conditions 2.5 - 3.0 V 0.5 - - - 0 - - - - - - 0.4 1000 300 400 V V ns ns kHz CL = 400 pF IL = 3 mA MICRONAS INTERMETALL 19 TPU 3035, TPU 3040 3.6.15. DRAM Interface Characteristics Symbol VIL VIH VOL VOH tT Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Transition Time 3 to 18 Pin No. 3 Min. - 2.0 - 2.4 - Typ. - - - - 5 Max. 0.8 - 0.4 - 10 PRELIMINARY DATA SHEET Unit V V V V ns Test Conditions IL = 1.6 mA IL = *0.5 mA CL = 15 pF VOL(max) VOH(min) 3.6.15.1. Fast Mode Timing at fCLK = 20.25 MHz Symbol tPC tCAS tCP tRP tRSH tCSH tRCD tCRP tASR tRAH tAR tRAL tASC tCAH tRRH tRCH tWCH tWCS tDOHR tDOS tDOH tDIS tDIH Parameter Page Mode Cycle Time CAS Pulse Width CAS Precharge Time RAS Precharge Time RAS Hold Time CAS Hold Time RAS to CAS Delay Time CAS to RAS Precharge Time Row Address Setup Time Row Address Hold Time Column Address Hold Time Column Address Lead Time Column Address Setup Time Column Address Hold Time Read Command Hold Time Read Command Hold Time Write Command Hold Time Write Command Setup Time DATA Output Hold Time DATA Output Setup Time DATA Output Hold Time DATA Input Setup Time DATA Input Hold Time 3, 5 3, 6 4, 5 4, 6 6, 7 to 18 5, 7 to 18 5 5, 6 Pin No. 6 60 10 90 30 110 25 10 0 15 90 55 0 25 10 0 25 0 90 0 25 20 0 Min. Typ. 98.8 60 10 90 40 110 45 55 55 15 105 55 5 60 80 50 90 30 105 0 60 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions 20 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 3.6.15.2. Slow Mode Timing at fCLK = 20.25 MHz Symbol tPC tCAS tCP tRP tRSH tCSH tRCD tCRP tASR tRAH tAR tRAL tASC tCAH tRRH tRCH tWCH tWCS tDOHR tDOS tDOH tDIS tDIH Parameter Page Mode Cycle Time CAS Pulse Width CAS Precharge Time RAS Precharge Time RAS Hold Time CAS Hold Time RAS to CAS Delay Time CAS to RAS Precharge Time Row Address Setup Time Row Address Hold Time Column Address Hold Time Column Address Lead Time Column Address Setup Time Column Address Hold Time Read Command Hold Time Read Command Hold Time Write Command Hold Time Write Command Setup Time DATA Output Hold Time DATA Output Setup Time DATA Output Hold Time DATA Input Setup Time DATA Input Hold Time 3, 5 3, 6 4, 5 4, 6 6, 7 to 18 5, 7 to 18 5 5, 6 Pin No. 6 60 50 90 60 120 25 10 0 15 95 105 0 35 10 0 25 0 95 0 35 20 0 Min. Typ. 148 60 60 90 60 140 65 85 55 15 155 105 35 60 80 50 90 50 155 30 60 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions MICRONAS INTERMETALL 21 TPU 3035, TPU 3040 3.6.16. Waveforms VOH VOL tCSH tRAL PRELIMINARY DATA SHEET WE tRRH tWCH RAS VOH VOL tRCD tAR tCP tPC tCAS tRSH tRCH tRP CAS VOH VOL VOH tWCS tCRP tRAH tASC tCAH tASR COLUMN ADDR. 1 COLUMN ADDR. 7 A[0...11] VOL ROW ADDR. COLUMN ADDR. 0 tDOHR tDOS tDOH DOUT VOH VOL VOH VOL VALID DATA VALID DATA VALID DATA tDIS tDIH DIN VALID DATA VALID DATA Fig. 3-15: DRAM page mode waveforms XTAL1 CLK 2 ns 14 ns MAC Input 15 ns Prio & Color Output 11 ns Prio & MSync Input 1 ns 5 ns Fig. 3-16: TPU 3040 Timing 22 MICRONAS INTERMETALL EEE EEE VALID DATA EEE EEE EEE EEE EEE EEE EEE EEE ROW ADDR. EE EE PRELIMINARY DATA SHEET TPU 3035, TPU 3040 4. Definitions 4.1. CPU 4.1.1. Memory Mapping Table 4-1: 65C02 memory map Interrupt Vector IRQ Reset NMI Control Word Memory Segment Program RAM Zero Page Stack Page OSD Buffer I/O Page Character ROM Program ROM Absolute Address (high byte, low byte) FFFF, FFFE FFFD, FFFC FFFB, FFFA FFF9 Absolute Address 0000 - 01FF 0000 - 00FF 0100 - 01FF 0100 - 019F 0200 - 02FF 6000 - 7FFF E000 - FFFF ADR DATA BE DATA ADR Zero Page Stack Page I/O Page 8K Program ROM DMA Interface 65C02 RDY Fig. 4-1: 65C02 memory environment MICRONAS INTERMETALL IIIIII IIIIII 8K Character ROM IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII Display BUSREQ 23 TPU 3035, TPU 3040 4.2. I2C Bus Interface Communication between TPU 3040 and host controller is done via I2C-bus. For detailed information on the I2Cbus please refer to the Philips manual `I2C-bus Specification'. The TPU 3040 acts as a slave transmitter/receiver and uses clock synchronization to slow down the data transfer if necessary. General call address will not be acknowledged. Different memories and functions of TPU 3040 can be accessed by subaddressing. The byte following the slave address byte is defined as the subaddress byte. Maximum length of an I2C telegram is 256 bytes following slave address and subaddress byte. The interface supports data transfer with autoincrement. The I2C-bus interface is interrupt-driven and uses an internal 48-byte buffer to collect I2C data in real-time without disturbing internal processes. This is done to avoid clock synchronization as far as possible. When the TPU 3040 has to process the I2C buffer and the I2C telegram has not yet been stopped, the I2C clock line will be held down. PRELIMINARY DATA SHEET The time required to process the I2C buffer depends on other processes running inside the TPU 3040 firmware. Thus the following I2C telegram addressing the TPU can be held after the slave address byte until the old telegram is completely processed. 4.2.1. Subaddressing Access to all memory locations and to the command interface is achieved by subaddressing. Both the external DRAM and the internal CPU memory can be addressed completely. The TPU 3040 acknowledges 6 different subaddresses following the slave address (see Table 4-2). The following symbols are used to describe the I2C example telegrams: < > ab ah al cc dd ss .. start condition stop condition address bank byte address high byte address low byte command byte data byte status byte 0 - n continuation bytes Table 4-2: I2C-bus Subaddresses Name TPU Sub 1 Sub 2 Sub 3 Sub 4 Data Status Binary Value 0010 001x 0111 1000 0111 1001 0111 1010 0111 1011 0111 1100 0111 1101 Hex Value 22, 23 78 79 7A 7B 7C 7D Mode W, R W W W W R/W R Function TPU slave address subaddressing CPU (static) subaddressing CPU (autoincrement) subaddressing DRAM (autoincrement) subaddressing command language subaddressing data register status register bit 7 = command wait bit 6 = command invalid bit 5 = command found no data bit 4 = not used bit 3 = not used bit 2 = not used bit 1 = 0 bit 0 = 0 24 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 When reading the DRAM, the first data byte the TPU 3040 returns is a dummy byte, which has to be ignored. < 22 7A ab ah al dd .. > < 22 7A ab ah al > < 22 7C dd .. > < 22 7A ab ah al > < 22 7C < 23 dd ..> Data written to the DRAM subaddress is collected first in the I2C buffer of TPU 3040 and is copied to DRAM when the buffer is full (48 bytes) or after stop condition. During the time the buffer is copied to DRAM the TPU 3040 will hold the I2C clock line down. Reading data from the DRAM subaddress is also buffered internally. Reading the first byte will only empty the I2C buffer. Every time the buffer is empty, the TPU 3040 will copy 48 bytes from DRAM into the I2C buffer. During this time the TPU 3040 will hold the I2C clock line down. 4.2.1.1. CPU Subaddressing There are 2 CPU subaddresses to access CPU memory: either with static memory address or with autoincrementing memory address. The main purpose of CPU subaddressing is to write text into the OSD buffer and to access the I/O page (see chapter 4.15.). The static CPU subaddress can be used to write more than 1 byte into the same I/O page register. The CPU subaddress has to be followed by 2 address bytes defining the CPU memory address. The following data byte is written into this address. In the case of autoincrement the continuation bytes are written into incrementing memory addresses. The CPU telegram can be stopped after the 2 memory address bytes. The following I2C telegram subaddressing the data register will continue data transfer to or from the CPU memory. The data transfer will always start at the CPU memory address (autoincrement is not saved). < 22 78 ah al dd .. > < 22 79 ah al dd .. > < 22 79 ah al > < 22 7C dd .. > Data is directly written into CPU memory without using the I2C buffer of TPU 3040 and without waiting for a stop condition. 4.2.1.3. Command Subaddressing TPU 3040 supports a command language, allowing the host controller to start complex processing inside the TPU 3040 with simple commands (see chapter 4.9.). Commands have to be sent to the command subaddress. The command subaddress has to be followed by the command code. The following data bytes are taken as command parameters. The execution time for commands depends on other processes running inside the TPU 3040 firmware, therefore the host controller has to read the status register to get information about the running command before reading command parameter or starting other commands. The status register returns information about the command interface. The `command wait' bit is set during execution of a command and is reset when a command is executed completely and read parameters are available. If a non-existing command is sent to the TPU 3040, the `command invalid' bit is set. If a command could not be executed successfully, the `command found no data' bit is set. In this case the read parameters of this command are not valid. Reading status from TPU 3040 is done by subaddressing the status register followed by repeated start condition and slave read address (see Fig. 4-3). < 22 7B cc dd .. > < 22 7D < 23 ss .. > < 22 7C < 23 dd .. > Telegrams subaddressing the command interface are buffered and processed after receiving the stop condition. Therefore the command code and all necessary command parameters have to be included in a single telegram. 25 4.2.1.2. DRAM Subaddressing DRAM access is necessary to generate level 2 displays. The external DRAM can be addressed on byte level. The maximum DRAM size of 16 Mbit requires a 21-bit memory address pointer. The format of the DRAM address pointer is shown in Fig. 4-2. III III III 5-bit Bank 8-bit High 8-bit Low Fig. 4-2: DRAM Address Pointer The DRAM subaddress has to be followed by 3 address bytes defining the DRAM address pointer. The following data byte is written into this address. DRAM subaddressing always uses autoincrement. Seperate read and write DRAM address pointers are saved for autoincrement. The DRAM telegram can be stopped after the 3 address pointer bytes. The following I2C telegram subaddressing the data register will continue data transfer to or from the DRAM. MICRONAS INTERMETALL TPU 3035, TPU 3040 4.2.1.4. Data Subaddressing Writing data to TPU 3040 memory is possible by subaddressing the data register directly. The data is then written into memory addressed by the foregoing telegram. < 22 7C dd .. > Reading data from TPU 3040 is done by subaddressing the data register followed by a repeated start condition and slave read address (see Fig. 4-3). The returned data depend on the subaddress selected in the preceding TPU telegram. < 22 7C < 23 dd .. > PRELIMINARY DATA SHEET S 0010001 W Ack 0111 1000 Ack n byte Sub 1 Ack P S 0010001 W Ack 0111 1001 Ack n byte Sub 2 Ack P S 0010001 W Ack 0111 1010 Ack n byte Sub 3 Ack P S 0010001 W Ack 0111 1011 Ack n byte Sub 4 Ack P S 0010001 W Ack 0111 1100 Ack n byte Data Ack P S 0010001 W Ack 0111 1100 Ack S 0010001 R Ack n-1 byte Data last byte Data Ack Nak P S 0010001 W Ack 0111 1101 Ack S 0010001 R Ack Status Status Ack Nak P SDA S SCL 1 0 P W R Ack Nak S P = = = = = = = = 0 1 0 1 Start Stop Interrupt Data from TPU Fig. 4-3: I2C-bus Protocol 26 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 4.3. Display Memory The TPU 3040 supports a variable number of display memories, each 4 KByte large. One bank is used to store the display information of the selected teletext page. The bank location can be defined with the command DISPLAY_TTX_POINTER. Other banks can be used to store any kind of display data in level 1 or level 2 format. Switching between these banks is fast and can be programmed with the command DISPLAY_POINTER. Bank switching allows generation of OSD menus without affecting the teletext display. autoincrement Row 0 40 byte level 1 40-bit pointer 40 byte level 2 full row attr. Row 1 40 byte level 1 40-bit pointer 40 byte level 2 full row attr. Display Bank Row 46 40 byte level 1 40-bit pointer 40 byte level 2 full row attr. Row 0 40 byte level 1 40-bit pointer 40 byte level 2 full row attr. Row 1 40 byte level 1 40-bit pointer 40 byte level 2 full row attr. TTX Display Bank Row 25 40 byte level 1 40-bit pointer 40 byte level 2 full row attr. Fig. 4-4: Display Memory Organization MICRONAS INTERMETALL 27 IIIIIIII IIIIIIII IIIIIIII IIIIIIII IIIIIIII DRAM TPU 3035, TPU 3040 Table 4-3: Full Row Attribute PRELIMINARY DATA SHEET Table 4-5: Level 2 Parallel Attributes + 55H Bit 7 6 5 4 to 0 R/W Reset - - - - Full Row Attribute 7 6 0 0 1 1 1 1 1 1 1 1 1 5 0 1 0 1 1 1 1 1 1 1 1 4 3 2 Color Color L 0 1 1 0 0 1 1 1 0 Function Foreground Color Background Color Flash Mode Character Set Size Underline/Separated Inverted Conceal Window/Boxing Shadow Italic P P P P P P P P P P P 1 = row is displayed blank 0 = row is displayed using row data 1 = row is displayed in double height 0 = row is displayed in normal height 1 = row is displayed in level 2 mode 0 = row is displayed in level 1 mode 5-bit value defining full row background color Table 4-6: Flash Modes Table 4-4: Level 1 Spacing Attributes 4 Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Function Alpha Black Alpha Red Alpha Green Alpha Yellow Alpha Blue Alpha Magenta Alpha Cyan Alpha White Flash Normal Flash Off Boxing Off Boxing On Size Normal Size Double Height Size Double Width Size Double Mosaic Black Mosaic Red Mosaic Green Mosaic Yellow Mosaic Blue Mosaic Magenta Mosaic Cyan Mosaic White Conceal Contiguous Mosaic Separated Mosaic ESC Black Background New Background Hold Mosaic Release Mosaic set at set at set at set at set at set at set mosaic mode and d d foreground color of following li mosaic characters select G1 character t set set at set at double set at double set at select G0 lt character set Action Notes set alpha mode and d d foreground color of following l h l i alpha characters 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Table 4-7: Color Look-Up Table 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Shaded attributes are default at start of each display row. 28 II II II II II II II II II I III II IIIII III II IIIIIII IIIII I IIIIIII IIIIIII IIIIIII IIIIIII Flash 0 0 0 0 1 1 1 1 0 1 1 1 0 0 0 0 Set DH 0 1 0 1 0 1 DW U I C S W IT CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC Function 3 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 2 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 x x 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x x Function Off Normal Normal Fast Phase 1 Normal Fast Phase 2 Normal Fast Phase 3 Inverted Inverted Fast Phase 1 Inverted Fast Phase 2 Inverted Fast Phase 3 Color Table Color Table Phase 1 Color Table Phase 2 Color Table Phase 3 Incremental Decremental 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 x 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 x Display Color Black Red Green Yellow Blue Magenta Cyan White Transparent Reduced Red Reduced Green Reduced Yellow Reduced Blue Reduced Magenta Reduced Cyan Reduced White Programmable MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 4.4. OSD Layer Table 4-8: OSD Layer Control Codes Code 01 02 03 04 05 06 07 08 0C 0D 0E - 7F 80 - FF Function Underline On Underline Off Flash On Flash Off Italics On Italics Off Transparent Shadow END CR ASCII Character Color Control layer becomes transparent layer becomes transparent and contrast is reduced to 66% end of layer end of text line using font 1 or font 2 only one control code per character is allowed bit 0 = foreground color blue bit 1 = foreground color green bit 2 = foreground color red bit 3 = background color blue bit 4 = background color green bit 5 = background color red bit 6 = replace white by transparent bit 7 = 1 Notes only for 13 scanlines/character Shaded attributes are default at start of each text line. MICRONAS INTERMETALL 29 TPU 3035, TPU 3040 4.5. Character Set 10-bit Character Code 000H PRELIMINARY DATA SHEET 080H 100H 180H 200H 280H 300H 380H Fig. 4-5: Character Set Organisation 30 IIIIIIII IIIIIIII G0 G0 G0 National National National National Character ROM PAL = 5200 byte IIIIIIII IIIIIIII G1 G0 G1 National National National National Mapping ROM 32 x 5 bit G2 G2 G2 User User User User G0 G0 G0 G1 G1 User National National National National G2 G2 G2 IIIIIIII IIIIIIII IIIIIIII IIIIIIII G3 G3 G3 User User User User NTSC = 2240 byte NTSC G0 NTSC G0 NTSC G0 NTSC G1 NTSC G1 NTSC User NTSC National 32 char MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 4.6. Font Structure MSB 9 Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10 LSB 0 Character Font Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10 Line 1 Line 2 Line 3 Line 4 `@` `@` `@` `@` `@` `@` `@` `@` `@` `@` `A` `A` `A` `A` Char 10 ROM_Adr = Char x 10 + Line + Font_Adr Line 4 Font_Adr 16 ROM_Adr 16 4 12-bit 2 14-bit 16-bit Extension Font Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10 Line 1 Line 2 Line 3 Line 4 `@` `@` `@` `@` `@` `@` `@` `@` `@` `@` `D` `D` `D` `D` `A` `A` `A` `A` `A` `A` `A` `A` `A` `A` `E` `E` `E` `E` `B` `B` `B` `B` `B` `B` `B` `B` `B` `B` `F` `F` `F` `F` `C` `C` `C` `C` `C` `C` `C` `C` `C` `C` `G` `G` `G` `G` Char 8 ROM_Adr = Char / 4 x 10 + Line +Ext_ Font_Adr Line 4 Ext_Font_Adr 16 ROM_Adr 16 4 10-bit 2 12-bit 16-bit Fig. 4-6: Character Font Structure MICRONAS INTERMETALL 31 TPU 3035, TPU 3040 4.7. Character Font PRELIMINARY DATA SHEET Table 4-9: G0 font 0 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 = National Option Table 4-10: National font 0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 32 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 Table 4-11: G1 font 0 0 1 2 3 4 5 6 7 = National Option 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MICRONAS INTERMETALL 33 TPU 3035, TPU 3040 Table 4-12: G2 font 0 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11 PRELIMINARY DATA SHEET 12 13 14 15 Table 4-13: User font 0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 34 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 Table 4-14: NTSC national font 0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Table 4-15: NTSC user font 0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MICRONAS INTERMETALL 35 TPU 3035, TPU 3040 4.8. Character Mapping Table 4-16: Character set options Option Bits C14,C13,C12 000 001 010 011 100 101 110 111 6 English French Swedish Czech German Spanish Italian English 38 Polish French Swedish Czech German Serbian Italian English PRELIMINARY DATA SHEET Character Set 40 English (US) French Swedish Czech German Spanish Italian English 55 English French Swedish Turkish German Spanish Italian English 70 English (US) Slovakian Hungarian Serbian Albanian Polish Turkish Rumanian Table 4-17: National option mapping Language 2/3 Albanian Czech English English (US) French German Hungarian Italian Polish Rumanian Serbian Slovakian Spanish Swedish Turkish 5/15 5/15 2/3 5/15 9/3 5/15 5/15 2/3 5/15 5/15 5/15 5/15 9/0 5/15 13/6 2/4 2/4 12/9 2/4 2/4 8/1 2/4 9/2 2/4 14/3 14/1 2/4 12/9 2/4 14/1 10/13 4/0 13/12 13/13 4/0 4/0 8/5 15/0 9/14 9/3 13/15 10/14 13/12 13/13 9/15 9/14 10/8 5/11 13/2 10/11 5/11 14/4 9/1 8/13 8/4 14/0 13/8 10/5 13/2 10/11 8/3 8/13 14/14 5/12 12/12 12/13 5/12 13/5 9/7 8/14 8/14 9/0 12/7 14/14 12/12 12/13 9/3 8/14 8/14 G0/G1 Table Position 5/13 12/3 12/11 5/13 15/4 8/2 8/15 10/1 5/13 15/8 14/11 12/3 12/11 8/4 9/13 8/0 5/14 11/12 8/4 5/14 14/6 8/8 14/6 12/15 5/14 13/3 10/6 11/12 8/4 9/4 8/15 8/15 5/15 9/1 15/13 5/15 13/0 5/15 13/0 11/15 5/15 9/4 15/1 13/0 15/13 9/2 13/0 10/12 6/0 13/13 9/3 6/0 14/7 9/5 14/0 9/3 8/2 10/9 10/15 13/13 9/3 9/9 9/3 15/1 7/11 13/3 8/3 7/11 14/5 8/7 8/10 9/4 8/5 13/9 8/7 13/3 8/3 8/12 8/10 14/15 7/12 12/13 12/0 7/12 15/6 9/8 8/11 8/11 9/6 13/7 14/15 12/13 12/0 9/11 8/11 8/11 7/13 13/1 9/2 7/13 15/5 8/9 8/12 8/3 9/5 15/9 12/5 13/1 9/2 9/5 9/12 9/0 7/14 11/13 11/13 7/14 15/7 9/0 9/10 8/12 8/6 13/11 8/8 11/13 11/13 8/5 8/12 8/12 36 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 4.9. Command Language Table 4-18: Command Table Code 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Code 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 Command Name Dummy Reset Escape Version Test Test DRAM Mode Acquisition Mode Display Mode Display TTX Pointer Display Pointer Display Clear Page Request Display Time Pointer Read DRAM Size Read VPS Read Quality Read Display Mode Read Reset Source Read Rolling Header Read Page Info Read Page Row Change Page Info Search MPET Read Display Page Page Memory Display Page Request Page Table Reset Search Next Page Read Page Cycle Read TOP Code Read Rolling Time Copy Page Row Copy Data Search Next TOP Code Read Ghost Row Read 8/30 Row Read Priority Page Priority Search AIT Read TOP Status Search AIT Title Reset Ghost Row Status Search MPT Copy AIT Title Search Direct Choice Read Hamming Read Hamming 2 Display Column Display Fill Read BTTL Read Next Page Change BTT magazine Read WSS Read CAPTION 1 Read CAPTION 2 OSD Font Pointer No. Write Parameter 0 0 0 0 0 0 3 5 3 2 3 2 8 2 0 0 0 0 0 0 2 5 3 0 0 2 5 0 3 0 2 0 8 7 3 6 1 0 2 0 0 2 0 0 5 1 1 3 3+length 4 0 2 1 0 0 0 5 No. Read Parameter 0 0 0 2 0 0 0 2 0 0 0 0 3 0 2 15 4 3 1 24 7 40 0 1 + (n*4) 4 0 0 0 6 9 2 8 0 0 4 40 40 5 0 1 + (n*4) 2 17 0 1 + (n*4) 17 1 + (n*2) 1 3 0 0 9 2 0 15 7 7 0 Status Register x000 0000 x000 0000 x000 0000 x000 0000 x000 0000 x000 0000 x000 0000 x000 0000 x000 0000 x000 0000 x000 0000 x000 0000 x0x0 0000 x000 0000 x000 0000 x0x0 0000 x000 0000 x000 0000 x000 0000 x000 0000 x000 0000 x0x0 0000 x000 0000 x0x0 0000 x000 0000 x000 0000 x000 0000 x000 0000 x0x0 0000 x000 0000 x000 0000 x000 0000 x0x0 0000 x000 0000 x0x0 0000 x0x0 0000 x0x0 0000 x000 0000 x000 0000 x0x0 0000 x000 0000 x0x0 0000 x000 0000 x0x0 0000 x0x0 0000 x0x0 0000 x000 0000 x000 0000 x000 0000 x000 0000 x0x0 0000 x000 0000 x000 0000 x0x0 0000 x0x0 0000 x0x0 0000 x000 0000 MICRONAS INTERMETALL 37 TPU 3035, TPU 3040 PRELIMINARY DATA SHEET Note: If not otherwise designated, all parameters in the following table are specified as single bytes. As write parameter magazine numbers 8 and 0 have the same meaning, as read parameter the magazine number is a true 4-bit number (e.g. magazine 8 = 00001000). For write parameters the values in parentheses indicate default values after reset (in hex notation). For compatibility reasons every undefined bit in a write parameter should be set to `0'. Undefined bits in a read parameter should be treated as "don't care". Table 4-19: Command Codes Code 00 01 02 03 04 05 06 Function Dummy Reset Escape Version Test Test DRAM Mode dram mode flash inc control enable (06) (05) (FF) CPU pointer high CPU pointer low Write Parameter Read Parameter Notes no action software reset of 65C02 escape to other codes show version in OSD layer CPU pointer to text in ROM reserved for testing reserved for testing dram mode = I/O page register 028EH flash freq = flash inc / (256 * 0.00324) control enable: bit0 = C4 erase page bit1 = C5 news flash bit2 = C6 subtitle bit3 = C7 suppress header bit4 = C8 update indicator bit5 = C9 interrupted sequence bit6 = C10 inhibit display bit7 = C11 magazine parallel gain filter acquisition mode: bit0 = no slicer adaption bit1 = no bit error in framing code bit2 = limit slicer adaption init subcode: automatic subcode request after page table reset gain max: only used if bit2 = 1 filter max: only used if bit2 = 1 dram size: 0080H = 256Kbit 0200H = 1Mbit 0800H = 4Mbit 2000H = 16Mbit start of page memory execute page table reset reset page table reset ghost row status reset data service status reset cycle count reset memory count reset ghost count reset priorities clear rolling header clear VPS data clear WSS data ghost row status: bit0 = row 24 in cycle bit1 = row 25 in cycle bit2 = row 26 in cycle bit3 = row 27 in cycle bit4 = row 28 in cycle bit5 = row 29 in cycle bit6 = row 30 in cycle bit7 = row 31 in cycle Operational & Test Commands 07 Acquisition Mode acquisition mode init subcode high init subcode low gain max filter max (00) (FF) (FF) (1F) (1F) Memory Management Commands 14 Read DRAM Size dram size high dram size low (slow mode) (fast mode) (fast mode) (fast mode) 25 27 Page Memory Page Table Reset dram bank dram high (00) (40) 42 Reset Ghost Row Status 38 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 Command Codes, continued Code 29 Function Read Page Cycle Write Parameter Read Parameter ghost row status 2 byte cycle count 2 byte memory count 2 byte ghost count data service status memory status Notes = number of pages in cycle = number of pages in memory = number of ghost blocks in memory data service status: bit0 = 8/30 format 1 updated bit1 = 8/30 format 2 updated bit2 = VPS updated bit3 = WSS updated bit4 = CAPTION 1st field updated bit5 = CAPTION 2nd field updated memory status: bit0 = memory full enable: bit0 = enable priority manager border: min/max border for page priorities highest priority lowest priority border priority magazine number page number = max priority in page memory = min priority in page memory = min/max border for page priorities = page with lowest priority 38 Page Priority enable border (00) (FF) 37 Read Priority Page Related Commands 12 Page Request magazine number page number page subcode high page subcode low priority quantity start magazine number start page number number of open requests removed magazine number removed page number remove pages from memory beginning at start page if page priority is disabled, ignores start page if page priority is enabled magazine number: bit0-3 = magazine number bit4 = not used bit5 = hex request bit6 = backward request bit7 = forced request = ignore cycle flag = pointer from page table = number of subpages in chain = number of ghost rows in chain if page request with subcode F1xx 20 Read Page Info magazine number page number page pointer high page pointer low subpage count ghost row count ring buffer index page subcode high page subcode low 22 Change Page Info magazine number page number page table flags page table flags: bit0 = protection bit1 = update bit2 = not used bit3 = not used bit4 = not used bit5 = subpage bit6 = memory bit7 = cycle magazine number page number page pointer high page pointer low subpage count ghost row count search in page table for cycle flag magazine number: bit0-3 = magazine number bit4 = take search code bit5 = hex search bit6 = backward search bit7 = include start page search code: bit0 = search protection flag bit1 = search update flag bit2-4 = not used bit5 = search subpage flag bit6 = search memory flag bit7 = search cycle flag calculate next page number magazine number: bit0-3 = magazine number bit4 = not used bit5 = hex calculation bit6 = backward calculation bit7 = not used 28 Search Next Page magazine number page number search code 51 Read Next Page magazine number page number magazine number page number MICRONAS INTERMETALL 39 TPU 3035, TPU 3040 Command Codes, continued Code 21 Function Read Page Row Write Parameter magazine number page number subpage number high subpage number low row number magazine number page number subpage number high subpage number low row number destination dram bank destination dram high destination dram low magazine number page number subpage number high subpage number low row number designation code 40 byte row data Read Parameter 40 byte row data PRELIMINARY DATA SHEET Notes row 0 - 24 32 Copy Page Row copy 40byte text row from page memory into DRAM 35 Read Ghost Row row 25 - 28 TOP Commands 40 Read TOP Status TOP status 1 TOP status 2 TOP status 1: bit0 = not used bit1 = MPT link in PLT bit2 = MPET link in PLT bit3 = AIT link in PLT bit4 = BTT in memory bit5 = MPT in memory bit6 = MPET in memory bit7 = AIT in memory TOP status 2: bit0-5 = not used bit6 = all MPET in memory bit7 = all AIT in memory code: bit0-3 = data bit6 = hamming error BTTL error: bit6 = hamming error in BTTL BTTL data: bit0-3 = data bit6 = hamming error all TOP commands then refer to this magazine number of MPTs magazine number page number subpage number high subpage number low ... number of MPETs magazine number page number subpage number high subpage number low ... number of AITs magazine number page number subpage number high subpage number low ... magazine number page number 5 byte data 12 byte title search in PLT 30 Read TOP Code magazine number page number BTT code MPT code BTTL error 8 byte BTTL data 50 Read BTTL 52 43 Change BTT magazine Search MPT magazine number (01) 23 Search MPET search in PLT 39 Search AIT search in PLT 41 Search AIT Title search in AIT magazine number: bit0-3 = magazine number (0#8) bit4-6 = not used bit7 = ignore title language data: bit0-3 = data bit6 = hamming error 40 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 Command Codes, continued Code 44 Function Copy AIT Title Write Parameter magazine number page number destination dram bank destination dram high destination dram low Read Parameter 5 byte data 12 byte title Notes search in AIT and copy title into dram magazine number: bit0-3 = magazine number (0#8) bit4-6 = not used bit7 = ignore title language data: bit0-3 = data bit6 = hamming error search in BTT magazine number: bit0-3 = magazine number bit4-5 = not used bit6 = backward search bit7 = include start page code condition: low nibble = BTT code high nibble = search condition 0 = BTT code in low nibble 1 = BTT code # 0 2 = block page 3 = group page 4 = normal page 5 = subtitle page 6 = TV page 7 = block/TV page 8 = group/block/TV page 9 = subpage a = block/TV subpage b = group/block/TV subpage c = title page d = future page e = future page f = future page code: bit0-3 = BTT code bit6 = hamming error code flag: bit0 = subtitle page found bit1 = TV page found bit2 = block page found bit3 = group page found bit4 = normal page found bit5 = future page found bit6 = title page found bit7 = subpage found search in AIT 34 Search Next TOP Code magazine number page number code condition magazine number page number code code flag 45 Search Direct Choice direct choice code number of AIT entries magazine number page number ... MICRONAS INTERMETALL 41 TPU 3035, TPU 3040 Command Codes, continued Code 36 Function Read 8/30 Row Write Parameter designation code Read Parameter 40 byte row data PRELIMINARY DATA SHEET Notes only format 1 and 2 are supported 1st byte of row data is already hamming decoded = 51H = incremented every VPS reception = biphase decoded VPS bytes 3-15 = 78H = incremented every WSS reception = 102 WSS elements from group 1 on = incremented every reception in field 1 = 3x oversampling = incremented every reception in field 2 = 3x oversampling every row 0 in cycle using time pointer updated every VBI Miscellaneous Data Commands 15 Read VPS framing code counter 13 byte VPS data framing code counter 13 byte WSS data counter 6 byte CAPTION data counter 6 byte CAPTION data 24 byte rolling header 8 byte rolling time text lines hamming errors parity errors soft errors reset source 53 Read WSS 54 55 19 31 16 Read CAPTION 1 Read CAPTION 2 Read Rolling Header Read Rolling Time Read Quality 18 Read Reset Source reset source: bit0 = clock supervision bit1 = voltage supervision bit2 = watchdog all bits in reset source are reset after read hamming byte: bit0-3 = data bit6 = hamming error address: bit0-5 = address bit7 = hamming error mode: bit0-4 = mode data: bit0-6 = data copy data from DRAM to DRAM 46 Read Hamming hamming (8,4) byte data 47 Read Hamming 2 hamming (24,18) 1st byte hamming (24,18) 2nd byte hamming (24,18) 3rd byte address mode data 33 Copy Data source dram bank source dram high source dram low length destination dram bank destination dram high destination dram low 42 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 Command Codes, continued Code 17 Function Read Display Mode Write Parameter Read Parameter Notes display mode: bit0 = forced boxing bit1 = reveal bit2 = box bit3 = time hold bit4 = page hold bit5 = row 24 hold bit6 = row 25 hold bit7 = row 26 hold display mode: see above character set: 6,38,40,55,70 font: 0=PAL 1=NTSC page memory is copied to TTX pointer display starts at pointer using scroll counter as line offset clear display bank beginning at pointer (26 rows * 86 bytes) (20) (20) 8byte time string from packet x/00 is copied to time pointer magazine number: bit0-3 = magazine number bit4 = change display delay bit5 = display clear (on update) bit6-7 = not used subpage number: F0xx for rolling subpages display delay: delay after row 0 reception in steps of 3.24ms (255 = no update) only used if bit4 = 1 magazine number page number subpage number high subpage number low dram high dram low length byte list ... dram high dram low length character font mode (00) font pointer high font pointer low extension font pointer high extension font pointer low current page in display Display Commands display mode character set font 08 Display Mode display mode character set font dram high dram low dram high dram low scroll counter dram high dram low dram high dram low (00) (06) (00) (20) (00) (20) (00) (00) 09 10 Display TTX Pointer Display Pointer 11 13 26 Display Clear Display Time Pointer Display Page Request magazine number page number subpage number high subpage number low display delay (1E) 24 Read Display Page 48 Display Column write to dram with increment of 86 byte = number of bytes in list 49 Display Fill repeated write of 1 character to dram = number of repeated writes font mode: bit0 = 0 = reset OSD font 2 pointer bit0 = 1 = load OSD font 2 pointer with following parameters 56 OSD Font Pointer MICRONAS INTERMETALL 43 TPU 3035, TPU 3040 4.10. Memory Manager The Memory manager is the core of the internal TPU 3040 software. Most of the acquisition and display related functions are controlled by this management. PRELIMINARY DATA SHEET 4.11. Memory Organization The upper end of the memory is defined by the DRAM size, the lower end can be defined with the PAGE_MEMORY command. Default memory organisation is shown in Fig. 4-8. 20 00 00 = 16Mbit DRAM 08 00 00 = 4Mbit 02 00 00 = 1Mbit Page Memory n x 1 KByte 00 80 00 = 256Kbit Acquisition 00 40 00 Scratch Memory Display Bank 4 KByte 00 30 00 TTX Display Bank 4 KByte 00 20 00 Acquisition Scratch 4 KByte 00 10 00 Page Table Page Table Memory Manager Page Memory Display Memory Display Controller 4 KByte 00 00 00 Fig. 4-7: Memory Manager Fig. 4-8: Memory Organization 44 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 The cycle flag will be set as soon as this page is detected in the transmission cycle even if it cannot be stored in memory. Only if the page is really stored in memory, the memory flag will be set. The subpage flag will be set for every page in cycle if the page subcode is different from 0000H or 3F7FH. The update flag is set every time a page is stored and will be reset only for the display page after updating the display memory. A page with protection flag set will never be removed from memory. The memory manager uses page priorities to decide which pages should be stored or removed from memory. If no more memory is available, pages with lowest priority are removed automatically and the higher priority pages are stored at their place. By setting the page priority the programmer has control over the memory management. The page table is fully controlled by the memory manager and should never be written by external software. To change the page table flags the command CHANGE_PAGE_INFO can be used. 4.12. Page Table The memory management is based on a fixed size page table, which has entries for every hexadecimal page number from 100 to 8FF. The page table starts with page 800 and contains a 2-byte page pointer for every page. The page table can be read with the command READ_PAGE_INFO sending the page number and reading the 2-byte page pointer containing: - DRAM pointer - cycle flag - memory flag - subpage flag - update flag - protection flag The DRAM pointer gives the location where the page is stored in memory. The page size is fixed to 1 KByte, only ghost rows are allocated dynamically. Table 4-20: Page Table Format Index 000 001 ... 100 ... 1F0 ... 7FE 7FF end magazine 7 hexadecimal pages (e.g. TOP) Cycle Flag Memory Flag Subpage Flag 2-byte Page Pointer start magazine 8 11-bit DRAM Pointer Update Flag Protect Flag MICRONAS INTERMETALL 45 TPU 3035, TPU 3040 PRELIMINARY DATA SHEET priority status subcode req subcode in control language 4-11 12-14 row flag row flag row flag row flag ghost row pointer subpage pointer 0-7 8-15 16-23 24-31 8 byte packet x/00 packet x/01 8 byte 1 KByte page data packet x/24 24 byte mag page index subcode subcode high low Fig. 4-9: Page Format 46 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 Table 4-21: Ghost Row Identification Row Number Tag 000 001 010 Row empty row 25 row 26 row 27 row 28 row 29 row 30 row 31 4-bit designation code 3-bit row number 4.13. Ghost Row Organization Page-related ghost rows are stored in blocks of 128 byte. These ghost blocks are linked together using 2 byte ghost row pointers. The first pointer can be found in the basic page, all following pointers are part of the block header. A zero pointer indicates the end of the chain. ghost pointer Page Table page pointer 011 100 101 110 111 page 100 ghost pointer ghost block 0000 `aa' `aa' `aa' row 1 row 2 row 3 ghost row pointer ghost block Fig. 4-10: Ghost Row Organization 8 byte block header Every ghost block contains 3 ghost rows which can be identified by 3 row identification bytes in the block header. The row identification contains designation code and row number. The row number is reduced to a 3-bit tag. All ghost rows in one block belong to the same page. If the memory manager removes a page from memory, the linked ghost blocks will also be removed. 40 byte row 1 data 40 byte row 2 data 40 byte row 3 data Fig. 4-11: Ghost Block Structure MICRONAS INTERMETALL 47 TPU 3035, TPU 3040 4.14. Subpage Manager Any page in cycle can have a number of subpages, identified by subcode. In normal mode the subpage manager will acquire only one subpage of every requested page. This subpage can be any if subcode FFFF is requested or it will be selected according to the requested subcode. After a PAGE_REQUEST command with subcode F0xx, the subpage manager will acquire all subpages of the requested page. The subpages will be chained in the same order as they are transmitted, i.e. every new subcode will be added at the end of chain. The page table entry points to the subpage which was transmitted first after the page request. The READ_PAGE_INFO command will reply the page table pointer and the actual number of subpages in chain. After a PAGE_REQUEST command with subcode F1xx, the subpage manager will acquire all subpages of the requested page but will allocate only a limited amount of memory to store these subpages. The parameter "page subcode low" will define the length (in number of subpages) of a ring buffer in page memory which will hold the recently received subpages. In this case, the READ_PAGE_INFO command will return an index pointing to the most recently updated subpage in chain, together with the subcode of this page. The DISPLAY_PAGE_REQUEST command searches and displays a page according to the requested display subcode. The search starts from page table and continues through the subpage chain if there is any. A rolling header will be displayed if the requested subpage cannot be found in memory. A requested display subcode FFFF (don't care subcode) will only search and display the first subpage in chain, thus there is no rolling subpage anymore. A DISPLAY_PAGE_REQUEST command with subcode F0xx (follow subcode) will search and display the last received subpage in chain, thus it is possible to request all subpages in background while still showing rolling subpages in display. PRELIMINARY DATA SHEET Page Table page pointer subpage pointer page 100 subcode 0003 subpage pointer page 100 subcode 0001 0000 page 100 subcode 0002 Fig. 4-12: Subpage Organisation 48 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 4.15. I/O Page Definition Most hardware related functions of the TPU 3040 are controlled by memory mapped I/O of the 65C02. The following table lists all available registers. For a more detailed description of the I/O page registers see next section. The application software has access to the I/O page registers via I2C-bus using the CPU subaddresses SUB1 and SUB 2. Table 4-22: I/O Page Register Addr. 0200 H 0201 H 0202 H 0203 H 0204 H 0210 H 0211 H 0212 H 0213 H 0220 H 0221 H 0222 H 0223 H 0224 H 0225 H 0226 H 0250 H 0251 H 0252 H 0253 H 0254 H 0255 H 0256 H 025A H 025B H 0260 H 0261 H 0262 H 0264 H 0265 H 0266 H 0267 H 0268 H 0269 H 026A H 026B H 026C H 026D H 026E H 026F H 0270 H Mode R/W W W W R/W R/W R/W R W R/W W W R R R R W W W W W W W W R/W W W W W W W W W W W W W W W W W User Test Test Appl TPU Test TPU TPU TPU Appl TPU TPU Appl Appl Appl Appl Appl Appl Appl Appl Appl Appl Appl Appl Appl Appl Appl Appl Appl Appl Appl Appl Appl Appl Test Appl Appl Appl Appl TPU Appl TPU Reset 00 H 00 H 00 H 6C H 07 H - 00 H - 01 H FF H 3B H 0F H - - - - 04 H 07 H 00 H 37 H 60 H 4D H 07 H 35 H 00 H 0060 H 0128 H 16 H version 0138 H 0C H 0024 H 0F H 00 H 0128 H 011E H 00 H 00 H pal font 8F H 00 H Name Control Register Test Mode Standby Watchdog Supervision Interface Data Interface Status Interface Address Interface Mode Interrupt Source Interrupt Enable Interrupt & Timer Mode Timer Latch Low Timer Latch High Timer Count Low Timer Count High Clamping Start Blanking Stop Blanking Start Halfline Code Display Mode 1 Display Mode 2 Clamping Stop PRIO Mode FB Mode OSD Layer Vertical Start OSD Layer Vertical Stop OSD Layer Horizontal Start OSD Layer Text Pointer OSD Layer 2nd Color Start OSD Layer 2nd Color WST Layer Vertical Start WST Layer Horizontal Start OSD Test WST Layer Vertical Stop WST Layer Last Row RGB Mode Sync Mode Display Font Pointer Display Mode 3 Display Mode 4 Addr. 0271 H 0272 H 0273 H 0274 H 0280 H 0281 H 0282 H 0283 H 0284 H 0285 H 0286 H 0287 H 0288 H 0289 H 028A H 028B H 028C H 028D H 028E H 0290 H 0291 H 0292 H 0293 H 0294 H 0295 H 0296 H 0297 H 0298 H 0299 H 029A H 029B H 029C H 029D H 029E H 029F H 02A0 H 02A1 H 02A2 H 02A3 H 02A4 H Mode W W W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W W W W W W W W W R R W W R W R W W W W W R User Test Test TPU Test TPU TPU TPU TPU TPU TPU TPU TPU TPU TPU TPU TPU TPU TPU TPU TPU Appl Appl Appl Appl TPU TPU TPU TPU TPU Test Test TPU TPU Appl Appl TPU Test Test Appl Appl Reset 00 H 00 H 00 H 00 H 00 H 20 H 00 H 00 H 10 H 00 H - - - - - - - - 06 H 01 H BE H 0A H FA H 09 H 07 H 0D H 04 H - - 00 H 00 H - 0F H - 18 H 50 H 00 H 00 H 00 H - Name Display Test 1 Display Test 2 Display Mode 5 Display Test 4 DRAM Display Pointer Low DRAM Display Pointer Medium DRAM Display Pointer High DRAM Slicer Pointer Low DRAM Slicer Pointer Medium DRAM Slicer Pointer High DRAM CPU Write Pointer Low DRAM CPU Write Pointer Medium DRAM CPU Write Pointer High DRAM CPU Read Pointer Low DRAM CPU Read Pointer Medium DRAM CPU Read Pointer High DRAM Data DRAM Hamming Data DRAM Mode ACQ Soft Slicer ACQ TTX Bitslicer Frequency Low ACQ TTX Bitslicer Frequency High ACQ VPS Bitslicer Frequency Low ACQ VPS Bitslicer Frequency High ACQ Filter Coefficient ACQ Data Slicer ACQ Accumulator Mode ACQ AC Accumulator ACQ FLT Accumulator ACQ Packet Header Low ACQ Packet Header High ACQ Soft Error Counter ACQ Sync Slicer ACQ Sync Status ACQ Standard ACQ Analog Mode ACQ Test Mode ACQ Test Observe ACQ Video Input ACQ HSync Counter Reset values are written by TPU during initialization. Application software should only write into registers with user label `Appl'! Most of the I/O page registers are only write registers and will not return useful data when read by application software. MICRONAS INTERMETALL 49 TPU 3035, TPU 3040 4.16. I/O Page Register PRELIMINARY DATA SHEET Note: For compatibility reasons, every undefined bit of a write register should be set to `0'. Undefined bits of a read register should be treated as "don't care". 0200 H Bit all R/W Reset 00 H CONTROL REGISTER Function During reset the control register is loaded with the contents of the address FFF9H, but it can be read and written via software. 1 = CPU disable 0 = CPU enable 1 = program RAM disable 0 = program RAM enable 1 = program ROM disable 0 = program ROM enable 1 = character ROM disable 0 = character ROM enable 1 = DMA interface disable 0 = DMA interface enable 1 = I/O page disable 0 = I/O page enable 1 = test mode on 0 = test mode off write: 1 = burnin test mode (only if test pin high) 0 = normal test mode read: 1 = burnin test mode 0 = normal test mode 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 0202 H Bit 2 Write Reset 0 STANDBY Function 1 = digital circuitry power off 0 = digital circuitry power on 1 = analog circuitry power off 0 = analog circuitry power on 1 = character ROM power off 0 = character ROM power on (CPU still active with slow clock) 1 0 0 0 0203 H Bit all Write Reset 6C H WATCHDOG Function reset watchdog if 8-bit value= 0x6c is written into this register all other values or time out will reset the chip 50 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 0204 H Bit 4 R/W Reset 0 SUPERVISION Function write enable only if test pin high write: 1 = short reset pulse 0 = long reset pulse write enable only if test pin high write: 1 = short watchdog period 0 = long watchdog period write enabled per mask option write: 1 = watchdog enable 0 = watchdog disable write disabled per mask option write: 1 = voltage supervision enable 0 = voltage supervision disable write disabled per mask option write: 1 = clock supervision enable 0 = clock supervision disable (15-bit FOSC) 3 0 (19-bit PH2) reset after read read: 1 = watchdog alarm 0 = watchdog sleeping reset after read read: 1 = voltage supervision alarm 0 = voltage supervision sleeping reset after read read: 1 = clock supervision alarm 0 = clock supervision sleeping 2 1 1 1 0 1 0210 H Bit all R/W Reset - INTERFACE DATA Function 8-bit value 0211 H Bit 7 6 5 4 3 2 1 0 R/W Reset - - - - - - - - INTERFACE STATUS Function write: write: write: write: write: write: write: write: 1 = reset interface (static) 0 = clear status read: read: read: read: read: read: read: read: 1 = stop condition 1 = write data telegram 1 = read data telegram 1 = sub 4 telegram 1 = sub 3 telegram 1 = sub 2 telegram 1 = sub 1 telegram 1 = start condition 0212 H Bit all Read Reset - INTERFACE ADDRESS Function 8-bit value MICRONAS INTERMETALL 51 TPU 3035, TPU 3040 PRELIMINARY DATA SHEET 0213 H Bit 2 Write Reset 0 INTERFACE MODE Function 1 = IIM Bus test enable (if normal test mode) 0 = IIM Bus test disable 1 = standby enable 0 = standby disable 1 = IIC Bus 0 = IIM Bus (if bit 2 of register 0202H = 1) 1 0 0 1 0220 H Bit all R/W Reset FF H INTERRUPT SOURCE Function write: 1 = reset interrupt source 0 = no action read: 1 = pending interrupt 0 = no pending interrupt 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 IR input falling edge IR input rising edge timer vertical sync display slave interface master interface TTX acquisition start TTX acquisition stop (bus write of address or read/write of data register) (bit 212 from timer = every 3.24ms) 0221 H Bit all Write Reset 3B H INTERRUPT ENABLE Function for bit mapping see register 0220 H 1 = interrupt enable 0 = interrupt disable 0222 H Bit 3 Write Reset 1 INTERRUPT & TIMER MODE Function 1 = timer not latched by falling edge of IR input (see Fig. 2-5) 0 = timer latched by falling edge of IR input 1 = timer not latched by rising edge of IR input (see Fig. 2-5) 0 = timer latched by rising edge of IR input 1 = IRQ generated by falling edge of IR input 0 = NMI generated by falling edge of IR input 1 = IRQ generated by rising edge of IR input 0 = NMI generated by rising edge of IR input 2 1 1 1 0 1 52 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 0223 H 0224 H 0225 H 0226 H Bit all Read TIMER LATCH LOW TIMER LATCH HIGH TIMER COUNT LOW TIMER COUNT HIGH Function 8-bit value (see Fig. 2-5) Reset - Timer Interrupt 212 fosc %16 16 bit counter 8 8 IR Interrupt IR D0...D7 Fig. 2-5: Timer Structure 0250 H Bit all Write Reset 04 H CLAMPING START Function horizontal start of clamping pulse in character increments (see Fig. 2-6) correct clamping pulse cannot be guaranteed if clamping start = clamping stop 0251 H Bit all Write Reset 07 H BLANKING STOP Function horizontal stop of blanking pulse in character increments (see Fig. 2-6) correct blanking pulse cannot be guaranteed if blanking start = blanking stop 0252 H Bit all Write Reset 00 H BLANKING START Function horizontal start of blanking pulse or self-timed HSYNC in character increments correct blanking pulse cannot be guaranteed if blanking start = blanking stop (see Fig. 2-6) 0256 H Bit all Write Reset 07 H CLAMPING STOP Function horizontal stop of clamping pulse in character increments (see Fig. 2-6) correct clamping pulse cannot be guaranteed if clamping start = clamping stop MICRONAS INTERMETALL 53 TPU 3035, TPU 3040 PRELIMINARY DATA SHEET HSYNC Clamping Blanking Fig. 2-6: Internal Timing 0253 H Bit all Write Reset 37 H HALFLINE CODE Function horizontal position to reset HSYNC flip-flop in normal sync mode (in character) horizontal position of halfline HSYNC in self-timed interlaced mode (in character) 0254 H Bit 7 Write Reset 0 DISPLAY MODE 1 Function 1 = OSD layer always uses FONT 1 0 = OSD layer changes from FONT 1 to FONT 2 if ASCII 20H 1 = enable OSD layer 0 = disable OSD layer 1 = active flash phase of OSD layer 0 = inactive flash phase of OSD layer 1 = 13 scanlines/character 0 = 8 scanlines/character With this scan line the OSD layer starts display of the first text line. By slow incrementing of this value soft scroll begins. 6 1 5 1 4 0 3 to 0 0 0255 H Bit 6 Write Reset 1 DISPLAY MODE 2 Function 1 = skew delay enable 0 = skew delay disable 1 = VSYNC active high 0 = VSYNC active low 1 = HSYNC active high 0 = HSYNC active low 1 = 10.125MHz display clock 0 = 20.25MHz display clock 1 = font pointer offset 10 scanlines/character 0 = font pointer offset 8 or 16 scanlines/character (depending on bit 1) 1 = font pointer offset 16 scanlines/character 0 = font pointer offset 8 scanlines/character 1 = 10 scanlines/character 0 = 8 or 13 scanlines/character (depending on bit 4 in register 0254 H) 5 0 4 0 3 1 2 1 1 0 0 1 54 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 025A H Bit 7 to 6 Write Reset 00 PRIO MODE Function prio output strength: 3 = 8 mA output pull-down current 2 = 6 mA output pull-down current 1 = 4 mA output pull-down current 0 = 2 mA output pull-down current 5 to 3 2 to 0 110 101 prio code for shadow pixel prio code for normal pixel 025B H Bit all 7 6 5 R/W Reset 00 H 0 0 0 FB Mode Function write: color bit 4 color bit 3 (color output of OSD layer) (color output of OSD layer) read: every read resets status 1 = inverted shadow output / enable fastblank input 0 = normal shadow output / disable fastblank input 1 = inverted color output 0 = normal color output 1 = inverted fastblank output 0 = normal fastblank output 1 = shadow output on pin 30 0 = fastblank input on pin 30 1 = invert fastblank input 0 = normal fastblank input 1 = fastblank input with high priority 0 = fastblank input with low priority read: dynamic fastblank status 4 0 3 0 2 0 1 0 0 0 read: static fastblank status 0260 H Bit all Write Reset 00 H 60 H OSD LAYER VERTICAL START Function 9-bit value defining vertical position (in scanline) 1st write: bit 0 = MSB 2nd write: bit7 to 0 = 8 LSBs 0261 H Bit all Write Reset 01 H 28 H OSD LAYER VERTICAL STOP Function 9-bit value defining vertical position (in scanline) 1st write: bit 0 = MSB 2nd write: bit7 to 0 = 8 LSBs 0262 H Bit all Write Reset 16 H OSD LAYER HORIZONTAL START Function 8-bit value defining horizontal start position (in character) MICRONAS INTERMETALL 55 TPU 3035, TPU 3040 PRELIMINARY DATA SHEET 0264 H Bit all Write Reset - OSD LAYER TEXTPOINTER Function 16-bit value defining memory address of text 1st write: bit7 to 0 = 8 MSBs 2nd write: bit7 to 0 = 8 LSBs 0265 H Bit all Write Reset 01 H 38 H OSD LAYER 2nd COLOR START Function 9-bit value defining vertical start for 2nd color (in scanline) 1st write: bit 0 = MSB 2nd write: bit7 to 0 = 8 LSBs 0266 H Bit 6 to 0 Write Reset 0C H OSD LAYER 2nd COLOR Function 7-bit value defining 2nd color 2nd color is used during 1 text row (8, 10 or 13 scanlines) after 2nd color start 0267 H Bit all Write Reset 00 H 24 H WST LAYER VERTICAL START Function 9-bit value defining vertical position (in scanline) 1st write: bit 0 = MSB 2nd write: bit7 to 0 = 8 LSBs 0268 H Bit all Write Reset 0F H WST LAYER HORIZONTAL START Function 8-bit value defining horizontal start position (in character) 026A H Bit all Write Reset 01 H 28 H WST LAYER VERTICAL STOP Function 9-bit value defining vertical position (in scanline) 1st write: bit 0 = MSB 2nd write: bit7 to 0 = 8 LSBs 026B H Bit all Write Reset 01 H 1E H WST LAYER LAST ROW Function 9-bit value defining last scanline of the last row to display level 1 double height after this scanline the level 1 double height attribute will not be decoded anymore 1st write: bit 0 = MSB 2nd write: bit7 to 0 = 8 LSBs 56 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 026C H Bit 6 Write Reset 0 RGB MODE Function 1 = inverted CLK20 input 0 = normal CLK20 input 1 = WST layer mixed mode 0 = WST layer normal mode 11 = WST layer top 10 = WST layer opaque bottom 01 = WST layer transparent bottom 00 = WST layer disable 1 = OSD layer mixed mode 0 = OSD layer normal mode 11 = OSD layer top 10 = OSD layer opaque bottom 01 = OSD layer transparent bottom 00 = OSD layer disable 5 0 4 to 3 0 2 0 1 to 0 0 026D H Bit 7 Write Reset 0 SYNC MODE Function 1 = MSYNC enable 0 = HSYNC & VSYNC enable 1 = CSYNC enable 0 = CSYNC disable 1 = double scan enable 0 = double scan disable 1 = blanking disable 0 = blanking enable 1 = NTSC self-timed mode 0 = PAL self-timed mode 1 = digital color mode enable 0 = digital color mode disable 1 = self-timed mode enable 0 = self-timed mode disable 1 = interlace enable = 312/313 0 = interlace disable = 312/312 (for self-timed mode only) (for self-timed mode only) 6 0 5 0 4 0 3 0 2 0 1 0 0 0 026E H Bit all Write Reset - DISPLAY FONT POINTER Function 4 x 16 value defining memory address of related font WST layer always uses font 1 order of loading: extension font 1 extension font 2 font 1 font 2 for every fontpointer: 1st write: bit7 to 0 = 8 MSBs 2nd write: bit7 to 0 = 8 LSBs MICRONAS INTERMETALL 57 TPU 3035, TPU 3040 PRELIMINARY DATA SHEET 026F H Bit 7 Write Reset 1 DISPLAY MODE 3 Function 1 = 10 pixel/character 0 = 8 pixel/character 1 = double dot size in vertical direction 0 = normal dot size in vertical direction 1 = double dot size in horizontal direction 0 = normal dot size in horizontal direction 1 = black colors replaced by transparent & shadow 0 = black colors displayed black (OSD layer only) 6 0 5 0 (OSD layer only) 4 0 (OSD layer only) 3 to 0 FH 4-bit value defining delay of horizontal start for both layers (in pixel) (leftmost position should not be used!) delay = mod16 (character_width - 2 - value) 0270 H Bit 2 Write Reset 0 DISPLAY MODE 4 Function 1 = boxing enable 0 = boxing disable 1 = reveal enable 0 = reveal disable This bit is taken as flash clock for the WST layer, the frequency should be around 6 Hz. 1 0 0 0 0273 H Bit 4 3 to 0 Write Reset 0 0 DISPLAY MODE 5 Function WST layer scan line counter preset (LSB for zoom mode) WST layer scan line counter preset 0280 H 0283 H 0286 H 0289 H Bit 7 to 0 R/W DRAM DISPLAY POINTER LOW DRAM SLICER POINTER LOW DRAM CPU WRITE POINTER LOW DRAM CPU READ POINTER LOW Function 8 least significant bits of 21 bit address pointer 12 LSBs of 21 bit address pointer are running with autoincrement read value is only specified when pointer is not incrementing Reset - 0281 H 0284 H 0287 H 028A H Bit all R/W DRAM DISPLAY POINTER MEDIUM DRAM SLICER POINTER MEDIUM DRAM CPU WRITE POINTER MEDIUM DRAM CPU READ POINTER MEDIUM Function 8 medium bits of 21 bit address pointer 12 LSBs of 21 bit address pointer are running with autoincrement read value is only specified when pointer is not incrementing writing this register clears all lower bits of related pointer Reset - 58 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 0282 H 0285 H 0288 H 028B H Bit 4 to 0 R/W DRAM DISPLAY POINTER HIGH DRAM SLICER POINTER HIGH DRAM CPU WRITE POINTER HIGH DRAM CPU READ POINTER HIGH Function 5 most significant bits of 21 bit address pointer static (no autoincrement) writing this register clears all lower bits of related pointer Reset - 028C H Bit all R/W Reset - DRAM DATA Function 8 bit value 028D H Bit all R/W Reset - DRAM HAMMING DATA Function 8 bit value writing this register resets hamming decoder 028E H Bit 4 Write Reset 0 DRAM MODE Function 1 = next CPU write without WEQ but with address increment 0 = normal CPU write mode 1 = reset address pointer and switch off refresh during standby 0 = keep address pointer and refresh during standby 1 = display channel enable 0 = display channel disable 1 = slicer channel enable 0 = slicer channel disable 1 = slow mode timing 0 =fast mode timing 3 0 2 1 1 1 0 0 0290 H Bit 4 to 0 Write Reset 01 H ACQ SOFT SLICER Function 5 bit binary soft slicer level is compared with ABS[data] (*32 data )31) 0291 H 0293 H Bit all Write Reset - ACQ TTX BITSLICER FREQUENCY LOW ACQ VPS BITSLICER FREQUENCY LOW Function 8 LSBs of bitslicer frequency MICRONAS INTERMETALL 59 TPU 3035, TPU 3040 PRELIMINARY DATA SHEET 0292 H 0294 H Bit 3 Write Reset 1 ACQ TTX BITSLICER FREQUENCY HIGH ACQ VPS BITSLICER FREQUENCY HIGH Function 1 = PHINC enable 0 = PHINC disable phase inc = Freq*(1)1/8) before framing code phase inc = Freq*(1)1/16) after framing code phase inc = Freq Freq = 211 * Bitfreq / 20.25MHz = 702 for PAL = 579 for NTSC = 506 for VPS or WSS = 153 for CAPTION 2 to 0 - 3 MSBs of bitslicer frequency 0295 H Bit 5 to 0 Write Reset 07 H ACQ FILTER COEFFICIENT Function high pass filter coefficient in 2's complement 100000 = not allowed 100001 = *31 000000 = 0 011111 = )31 0296 H Bit 5 to 0 Write Reset 0D H ACQ DATA SLICER Function 6-bit binary data slicer level is compared with ABS[data] (*32 data )31) 0297 H Bit 3 Write Reset 0 ACQ ACCUMULATOR MODE Function 1 = soft error correction disable 0 = soft error correction enable 1 = AC & FLT accu disable 0 = AC & FLT accu enable 1 = DC accu disable 0 = DC accu enable 1 = reset DC & AC & FLT accu 0 = no action (one shot) (only during VPS&CAPTION line) 2 1 1 0 0 0 0298 H 0299 H Bit all Read Reset - ACQ AC ACCUMULATOR ACQ FLT ACCUMULATOR Function 8 MSBs of 16bit accu accu increment is 6-bit binary ABS[data-slicer_level] these 8 MSBs are reset after read read must occur when accu is not active (*32 data )31) 029A H Bit all Write Reset 00 H ACQ PACKET HEADER LOW Function 8 LSBs of MAC packet address 60 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 029B H Bit 7 to 4 Write Reset 6 ACQ PACKET HEADER HIGH Function 4-bit framing code window every detected clock-runin loads window counter with 4-bit value * 2 (e.g. 6 12-bit window) window counter is clocked down to 0 with teletext bit rate slicer will ignore text line if no framing code is found inside framing code window 0000 = disable framing code window 1 = subframe 2 MAC packet acquisition enable 0 = subframe 2 MAC packet acquisition disable 1 = subframe 1 MAC packet acquisition enable 0 = subframe 1 MAC packet acquisition disable 2 MSBs of MAC packet address 3 0 2 0 1 to 0 0 029C H Bit 5 to 0 Read Reset - ACQ SOFT ERROR COUNTER Function 6-bit soft error counter counts number of soft error corrected bytes counter stops at 63 reset after read 029D H Bit 7 Write Reset 0 ACQ SYNC SLICER Function 1 = vertical sync window disable 0 = vertical sync window enable 7-bit binary sync slicer level is compared with binary data (0 data 127) 6 to 0 00 H 029E H Bit 7 Read Reset - ACQ SYNC STATUS Function 1 = field 1 0 = field 2 1 = vertical retrace 0 = vertical window set at line 624 (PAL) or line 524 (NTSC) reset at line 313 (PAL) or line 263 (NTSC) set at line 628 (PAL) or line 528 (NTSC) reset at line 624 (PAL) or line 524 (NTSC) 6 - MICRONAS INTERMETALL 61 TPU 3035, TPU 3040 PRELIMINARY DATA SHEET 029F H Bit 7 Write Reset 0 ACQ STANDARD Function 1 = CAPTION enable in field 2 0 = CAPTION disable in field 2 1 = CAPTION enable in field 1 0 = CAPTION disable in field 1 1 = VPS enable 0 = VPS disable VPS and CAPTION cannot be used at the same time, therefore these combinations are used to enable WSS reception on a PAL+ signal 0= 1 = VPS 2 = CAPTION field 1 3 = WSS & VPS 4 = CAPTION field 2 5 = WSS & VPS 6 = CAPTION field 1&2 7 = WSS 1 = TTX enable 0 = TTX disable 1 = MAC VBI channel A 0 = MAC VBI channel B 1 = MAC packet acquisition enable 0 = MAC VBI acquisition enable 1 = NTSC mode 0 = PAL mode 1 = MAC mode 0 = composite video mode MAC and NTSC cannot be used at the same time, therefore this combination is used to enable full VBI data reception in Caption mode 6 0 5 0 7 to 5 0 4 1 3 1 2 0 1 0 0 0 1 to 0 0 02A0 H Bit 7 Write Reset 0 ACQ ANALOG MODE Function 1 = full N clamping 0 = half N clamping 1 = N clamping disable 0 = N clamping enable 1 = clamping disable 0 = clamping enable 5 bit analog gain of AGC 31 = 12dB 16 = 6dB 00 = 0dB (*150 A) (* 75 A) (*150 A if data < sync slicer level) (+225 A if data = 0, *6 A static) 6 1 5 0 4 to 0 10 H 02A3 H Bit 0 Write Reset 0 ACQ VIDEO INPUT Function 1 = video input 2 0 = video input 1 (pin 44) (pin 42) 02A4 H Bit 7 to 0 Read Reset 0 ACQ HSYNC COUNTER Function number of detected horizontal sync pulses per frame divided by 4 sync pulse is detected if within horizontal window of HPLL counter is latched with vertical sync, the register can be read at any time 62 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 5 . Application 22pF 22pF 10nF 12 RASQ DATA A[0...11] CASQ WEQ VIN1 VIN2 100nF 10 F 2 x 75 VRT SGND TEST XTAL2 RIN 100nF GIN 100nF BIN FBIN 4 x 75 20.25Mhz XTAL1 100nF 256Kbit - 16Mbit DRAM 33nF 33nF TPU 3040 +5 V AVSUP 100nF AGND +5 V DVSUP 100nF DGND RESETQ 10k +5 V 100nF 1k IR SDA SCL HSYNC VSYNC FBOUT ROUT GOUT BOUT 1k 1k +5 V Fig. 5-1: TPU 3040 Application MICRONAS INTERMETALL 63 TPU 3035, TPU 3040 6. Emulator 6.1. EMU Additional Pin Connections Signal Name EMU Supply Voltage EMU Ground CPU Data Bus 7...0 CPU Address Bus 15...0 CPU Write Enable CPU Emu Disable CPU Reset CPU Bus Enable CPU Phase 2 Clock CPU Ready CPU Non-Maskable Interrupt CPU Interrupt Request OSD Data Bus 7...0 OSD Address Bus 15...0 OSD Emu Disable Type Supply Supply Input/Output Output Output Input Output Output Output Output Output Output Input Output Input Symbol EVSUP EGND PRELIMINARY DATA SHEET CPUDB[7...0] CPUADB[15...0] CPUWE CPUEDIS CPURES CPUBE CPUPH2 CPURDY CPUNMI CPUIRQ OSDDB[7...0] OSDADB[15...0] OSDEDIS 6.2. EMU Pin Configuration 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P 100 104 106 108 110 114 116 118 120 122 124 126 128 1 97 99 102 105 109 112 113 119 121 125 129 130 132 5 95 98 101 103 107 111 115 117 123 127 131 2 93 94 96 89 90 92 87 88 91 85 86 84 83 80 82 81 78 76 79 74 73 77 72 70 4 7 3 6 8 9 11 13 A B C D E F G H J K L M N P 10 12 15 Bottom View 16 14 17 18 20 19 25 22 21 26 24 23 30 28 27 75 69 68 65 61 57 51 49 45 41 37 35 32 29 71 66 64 63 59 55 53 47 46 43 39 36 33 31 67 62 60 58 56 54 52 50 48 44 42 40 38 34 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Fig. 6-1: EMU 3040 in 132-pin PGA package 64 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 6.3. EMU Pin Connections Bond Pin 1 2 3 4 5 6 7 8 9 A-1 Symbol SUBSTRAT COVER CAS Bond Pin 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 P-1 Symbol nc Bond Pin 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Symbol Bond Pin Symbol EEEEEEEEEEEEEEEEEEEEEEEEEE E E E E EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE E E E E E E E EEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEE E E E EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEE EEEEEEEEE E EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE E E EEEEEEEEE EEEEEEEEEEEEEEEEEE E EEEEEEEEE EEEEEEEEEE EEEEEEEEE E EEEEEEEEEEEEEEEEEEEEEEEEEE E EEEEEEEEEE E EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEE E E EEEEEEEEEE E EEEEEEEEE E EEEEEEEEEE EEEEEEEEEEEEEEEEE E EEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE E EEEEEEEEE E E EEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEE EEEEEEEEEEEEEEEEE E EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE E E E EEEEEEEEE E E E EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEE E E EEEEEEEEE E E EEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEE E EEEEEEEEEE EEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEEEEEEEEE E EEEEEEEEE EEEEEEEEE E E E E E E EEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEE E E E EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEE E E E E EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEE EEEEEEEEEEEEEEEEE E P-14 XTAL1 100 A-14 A9 C-3 C-2 D-3 B-1 M-3 N-3 CPUNMI M-12 OSDDB[6] M-13 XTAL2 101 C-12 OSDADB[6] 102 B-12 nc GOUT CPUDB[1] RAS M-4 P-2 CPUADB[7] L-12 OSDDB[5] N-14 VSYNC 103 C-11 OSDADB[5] 104 A-13 A8 BOUT D-2 E-3 E-2 CPUDB[0] nc N-4 P-3 CPUADB[6] nc L-13 OSDDB[4] K-12 nc 105 B-11 OSDADB[4] 106 A-12 nc CPUADB[11] nc M-5 P-4 CPUADB[5] K-13 OSDDB[3] M-14 nc 107 C-10 OSDADB[3] 108 A-11 A7 C-1 F-3 nc 10 11 CPUADB[10] WE N-5 P-5 CPUADB[4] nc J-12 OSDDB[2] L-14 HSYNC 109 B-10 OSDADB[2] 110 A-10 nc 111 C-9 D-1 F-2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 CPUADB[9] DATA M-6 N-6 N-7 P-6 CPUADB[3] J-13 OSDDB[1] OSDADB[1] A6 E-1 FBOUT K-14 MAC_SYNC H-13 OSDDB[0] J-14 nc 112 B-9 113 B-8 114 A-9 G-2 F-1 CPUADB[8] TEST CPUADB[2] DGND OSDADB[0] A5 G-3 G-1 H-3 H-1 H-2 J-1 J-2 EVSUP nc M-7 P-7 CPUADB[1] H-12 OSDADB[15] H-14 MAC_VBI 115 C-8 116 A-8 CPUPH2 nc DVSUP EGND VRT nc M-8 P-8 CPUADB[0] G-12 OSDADB[14] G-14 nc 117 C-7 118 A-7 119 B-7 120 A-6 121 B-6 122 A-5 CPURES A4 RIN N-8 P-9 CPUADB[15] nc G-13 OSDADB[13] F-14 MAC_PAK CPUIRQ A3 VIN2 nc N-9 CPUADB[14] F-13 OSDADB[12] E-14 IR CPUDB[7] nc K-1 K-2 J-3 SGND nc P-10 GIN M-9 CPUADB[13] E-13 OSDADB[11] F-12 SDA 123 C-6 124 A-4 125 B-5 126 A-3 CPUDB[6] nc VIN1 P-11 nc K-3 L-1 L-2 CPUEDIS AVSUP N-10 CPUADB[12] P-12 BIN E-12 OSDADB[10] D-14 nc CPUDB[5] A2 CPUBE nc M-10 CPUWE P-13 nc D-13 OSDADB[9] C-14 SCL 127 C-5 128 A-2 129 B-4 130 B-3 CPUDB[4] A1 M-1 L-3 CPURDY AGND nc N-11 OSDEDIS N-12 FBIN D-12 OSDADB[8] B-14 A11 CPUDB[3] A0 N-1 M-2 N-2 M-11 OSDDB[7] N-13 RESET C-13 OSDADB[7] B-13 A10 131 C-4 132 B-2 CPUDB[2] nc ROUT MICRONAS INTERMETALL 65 TPU 3035, TPU 3040 6.4. EMU I/O Page Definition Address 02E0 H 02E1 H 02E4 H Mode R/W R/W W Name PC Interface Data PC Interface Status EMU Led Port PRELIMINARY DATA SHEET 6.5. EMU I/O Page Register 02E0 H Bit all R/W Reset - PC INTERFACE DATA Function write: reset BUSY read: 8 bit data from centronics 02E1 H Bit 7 6 5 4 3 2 1 0 R/W Reset - - - - - - - - PC INTERFACE STATUS Function write: write/read: write/read: write/read: write/read: write/read: write/read: write/read: DOWN = green LED SDEM = yellow LED USERM = yellow LED ERROR = red LED = centronics pin 15 ACK = centronics pin 10 PE = centronics pin 12 SELECT = centronics pin 13 OUTEN read: BUSY = centronics pin 11 02E4 H Bit all Write Reset - EMU LED PORT Function general purpose port 66 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 6.6. EMU Board OSDEN EMU Logic OSDOE OSDWE CPUOE CPUWE 32kbyte CPU SRAM/EPROM 32kbyte OSD SRAM/EPROM CPUADB CPUDB OSDADB CPURES CPUWE CPUPH2 CPUEDIS OSDEDIS CPUPH2 EMU 3040 CPUIRQ CPUNMI CPUBE CPURDY RESET MAC TEST 3 TPU 3040 XTAL1 SDA SCL IR Clock Oscillator XTAL2 16Mbit DRAM TV Interface Fig. 6-2: EMU 3040 Board MICRONAS INTERMETALL 67 AA AA AA AA AA AA AA AA AA AA AA AA AA AA EE EE EE EE EE EE EE EE EE EE AAAAAAA AAAAAAA Control Bus Address Bus PC Interface Data Bus Bus Switch EE EE EE EE EE EE EE EE EE EE OSDDB TPU 3035, TPU 3040 7. Glossary of Abbreviations AIT BTT BTTL CEPT CLUT CPU CRI DRAM DRCS FLOF FRC MAC MPT MPET OSD PDC PLT RAM ROM TOP TPU TTX VBI VPS WSS WST Additional Information Table Basic TOP Table Basic TOP Table List Conference Europeene des Administrations des Postes et Telecommunication Color Look Up Table Central Processing Unit Clock Runin Dynamic Random Access Memory Dynamically Redefinable Character Set Full Level One Features Framing Code Multiplexed Analogue Components Multipage Table Multipage Extension Table On Screen Display Programme Delivery Control Page Linking Table Random Access Memory Read Only Memory Table Of Pages Teletext Processing Unit Teletext Vertical Blanking Interval Video-Programm-System Wide Screen Signalling World System Teletext 8. References 1) 2) PRELIMINARY DATA SHEET "World System Teletext and Data Broadcasting System". Technical Specification. February 1990. "Teletext Specification". Interim Technical Document SPB 492. European Broadcasting Union. December 1992. "8R2 Video-Programm-System (VPS)". Technische Richtlinie ARD/ZDF. "8R4 Fernsehtext-Spezifikation". Technische Richtlinie ARD/ZDF. "8R5 TOP-Verfahren fur Fernsehtext". Technische Richtlinie ARD/ZDF. "Specification of the domestic video Programme Delivery Control system (PDC)". European Broadcasting Union. August 1990. "Television systems; 625-Line television Wide Screen Signalling (WSS)". ETSI. November 1993. "Television Captioning for the Deaf". Signal and Display Specifications. May 1980. 3) 4) 5) 6) 7) 8) 68 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 MICRONAS INTERMETALL 69 TPU 3035, TPU 3040 PRELIMINARY DATA SHEET 70 MICRONAS INTERMETALL PRELIMINARY DATA SHEET TPU 3035, TPU 3040 MICRONAS INTERMETALL 71 TPU 3035, TPU 3040 9. Data Sheet History 1. Preliminary data sheet: "TPU 3040", Nov. 27, 1992, 6251-349-1PD. First release of the preliminary data sheet. 2. Preliminary data sheet: "TPU 3040", June 28, 1993, 6251-349-2PD. Second release of the preliminary data sheet. 3. Preliminary data sheet: "TPU 3040", Dec. 20, 1993, 6251-349-3PD. Third release of the preliminary data sheet. PRELIMINARY DATA SHEET 4. Preliminary data sheet: "TPU 3035, TPU 3040", Sept. 20, 1995, 6251-349-4PD. Fourth release of the preliminary data sheet. Major changes: - Combined data sheet for TPU 3035 and TPU 3040. 5. Preliminary data sheet: "TPU 3035, TPU 3040", Dec. 9, 1996, 6251-349-5PD. Fifth release of the preliminary data sheet. Major changes: - section 4.14.: subpage manager extension - section 4.16.: RGB mode bit 6 added MICRONAS INTERMETALL GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@intermetall.de Internet: http://www.intermetall.de Printed in Germany Order No. 6251-349-5PD All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery dates are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, MICRONAS INTERMETALL GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Reprinting is generally permitted, indicating the source. However, our prior consent must be obtained in all cases. 72 MICRONAS INTERMETALL End of Data Sheet Multimedia ICs MICRONAS Back to Summary Back to Data Sheets |
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